• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 28 subscribers
  • Views 358 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DLPC3433: Via limitiation on MIPI lines

Morgan Novak
Prodigy 235 points
Part Number: DLPC3433

My team is having a hard time routing the MIPI data lines (from DisplayPort to DLPC) on one plane.

In order to match p/n lengths, we can get it down to 2 vias  but not less.

Will this suffice or will 2 vias on a line cause too much signal disruption? 

Should we focus more on the p/n length match or less vias?

  • 0
    TI__Genius 10495 points

    Hello Morgan, 

    Please take a look at your DSI transceiver layout guidelines for matching requirements and max length requirements. 

    Generally p/n per pair should be closely matched as well as data pair to clock pair. This should be done independent of the needs of via's. All signals would need to follow the impedance requirements. 

    If via's need to be added, it is recommend to use the same amount of via's for p and n. 2x via's will probably be okay. A p/n pair should also be routed on the same layer. 

    We also recommend to do some signal integrity simulation if there are reasons for concerns. 

    Thanks,

    Nadine