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DLPLCRDC4422EVM: No image from FPGA (neither TPG nor Vx1 input)

Part Number: DLPLCRDC4422EVM
Other Parts Discussed in Thread: DLPC4422, DLP470TE

Hello all,

we want to set up the DLPLCRDC4422EVM with DLP470EVM to display an image from the V-by-one input. Image output from ASIC works fine (various patterns from TPG, Splash).


However, we see no image yet when connecting our own Vx1 source. We emit 600 MHz Pixel clock (not the often used 594), and the timing (freely programmable on our image source) matches Timing #3 (3840x2160_60) from DLP470TE_Vx1_Input_Video_Timings.xlsx. Colour depth is 10 bits per colour as supported by DLPC4422 EVM.  A 4k LC panel (InnoLux M280DGJ-L30) displays the test image correctly.

Next we tested the FPGA TPG and also don't see an image. Settings (applied via DLP GUI) are:

On the "Display" page, projection mode is set to "EXTERNAL".

On the "FPGA Control Page":

- FPGA UHD TPG is set to "240Hz_4XPR", then, unter "FPGA UHD Mode Status", both "Is XPR ON" and "Is TPG ON" are  checked.

- Tried different FPGA TPG Patterns, but no image with neither of them.

*** What looks strange to me is that on the "Source" page under "Source Desctiption":

-  "Active Display" is always "SFG", when changing this to "EXTERNAL", the "Datapath State" entry goes to "LOOK_FOR_SYNCS", and "Active Display" goes back to "SFG" after a few seconds.

I would assume that "Active Display" should be "EXTERNAL" when I set "EXTERNAL" as Projection Mode in the Display page, and "Datapath State" should be "MONITOR_SOURCE", is that correct?

Thank you for any advice on how to proceed,

Matthias

  • Addendum:  EVM firmware is V 9.4.1, FPGA version 0_0_147

  • Thank you Matthias. Our team will check out your setup and propose actions tomorrow.

    Regards,

    Matt

  • Hello Matthias,

    Sorry for the delay, we are running in to some issues while trying to recreate your use-case.

    The question about the 'Source' page has to do with a time-out related to waiting for input - this should be double-checked. There might be a software solution but we need to recreate it first.

    Please wait for updates.

    Best,

    Aaron Black

  • Hello Matthias,

    Please bear with us as we work on this, a short week and inclement weather are causing some delays.

    Best,

    Aaron Black

  • Hello Aaron,

    thank you for your message - no problem, we stay tuned.

    Best, Matthias

  • Thank you Matthias. We will be back in the lab soon and report out on the findings.

    Matt

  • Matthias,

    I just wanted to let you know that I have tried to see what I can do to help here.  I have acquired DMDs, DMD EVM boards, and the Dual-Controller 4422 EVM.  I am having trouble with the hardware and can't get the flash programmed for some reason.  I am not sure why we are having so much trouble here; this typically is not a problem. 

    In the mean time, let's confirm a few things.  Have you tried enabling the FPGA TPG first... FPGA Control -> FPGA UHD TPG -> XPR OFF 2D TPG 120Hz -> Set.  Then do a GET on "Is TPG ON".  After thais, set the Display Projection mode to EXTERNAL (Display -> Projection Mode -> EXTERNAL).  You can try setting the FPGA TPG to a different pattern that may be more obvious... FPGA Control -> FPGA General Configuration -> Test Patterns -> 7-Checkerboard.  Hopefully that displays a checkerboard on the DMD and helps confirm the FPGA/DLPC4422 interface is working... 

    Regards,
    Gary

  • Matthias,

    Were you able to try what Gary suggested.  Let us know the result and whether you need further assistance with this.

    Fizix

  • Hi Gary, thanks, I just tested as you described above, and now FPGA TPG works as intended with the procedure you suggested, using FPGA Control -> FPGA UHD TPG -> XPR OFF 2D TPG 120Hz -> Set (Checkerboard pattern visible).

    So we can proceed by testing with our Vx1 input signal, if we encounter further problems/questions, I'll open a new thread.

    Thank you so far for your help!

    Best,

    Matthias

  • Good news!  It is a bit tricky because the FPGA and Controller don't really talk to each other, so you need to get the source (FPGA TPG in this case) started before you tell the controller to look for an external input.  I am glad that works... hopefully that gets you one step closer to working.

    Thanks for the update.

     - Gary