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DLPC910: DLPC910

Moshe Levy
Prodigy 230 points
Part Number: DLPC910
Other Parts Discussed in Thread: DLPC410

Hello

1. Does the DLPC910 has power up and power down requirements? 

2. How does the DLPC910 power up is in relation to the DLPR910. who should ramp up first?

Thank you!

  • 0
    TI__Mastermind 48440 points

    Hello again Moshe,

    Good to hear from you.  

    1. Does the DLPC910 has power up and power down requirements? 

    The data sheet has very little regarding any power up sequencing.  There is a DLPC910 reference design that uses the output of some regulators to enable some of the other regulators.  As a starting point I would follow that design.  https://www.ti.com/tool/TIDA-00570 

    2. How does the DLPC910 power up is in relation to the DLPR910. who should ramp up first?

    The DLPC910 differs from the DLPC410 in this regard.  On the DLPC910, the FPGA runs the configuration clock, so that the PROM will wait until the FPGA starts the clock.  I do not know the entire handshake process, but if the PROM comes up first it will wait.  

    I hope this helps

    Fizix

  • +1 in reply to Fizix
    Prodigy 230 points

    Hi fizix,

    Very nice of you for the prompt and detailed reply as always.

    - regarding 1. i will look into the refernce design. i nparallel i checked with Xilinx and no power up sequence is needed.

    - regarding 2. makes sense to ramp the DLPR910 first and let it wait. again, verified with Xilinx and this is the recommended wat to do.

    cheers.

    ML