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Original question:

DLP9500UV: DMD Chip Product Selection

DLP9500: Availability of control boards

Dominic Mähling
Prodigy 10 points
Part Number: DLP9500
Other Parts Discussed in Thread: DLPLCRC410EVM, , ALP

Hello everybody,

we are planning on building a lithography setup using the DLP9500. Unfortunately, we were unable to purchase control boards like the recommended DLPLCRC410EVM due to no available stock for months.

Is it possible to use other control boards? We do need 8bit steady image only.

Thank you very much and best regards!

  • 0
    Intellectual 340 points

    Hi Dominic,

    we would be happy to help you with our DLP9500UV based setup (www.vialux.de/.../superspeed-specification.html) including the proven ALP Controller Suite. Also, thanks to our compact form factor, you can set up multiple boards side by side. Please contact us dlp@vialux.de

    Best, Phil

  • 0
    TI__Intellectual 1885 points

    Dominic

    I am sorry to report TI is still waiting on part shortages for the next build of our DLPLCRC410 EVM. 

    Another note you list the need for 8-bit imaging.

    The base DLPLCRC410EVM only operates with 1-bit patterns, at very high speeds.

    Any application needs for multi-bit images will need to be implemented in the  Applications FPGA (Virtex-5) that is on the DLPLCRC410EVM, by the purchaser.

     

  • 0 in reply to Robert from ViALUX
    Prodigy 10 points

    Hi Phil,

    Thank you for your reply! Is it possible to directly image 8bit grey scale patters with your modules? Could you please provide a price estimate on the DLP9500 (nonUV) and the DLP6500 version?

    Best regards

  • 0 in reply to Carey Ritchey
    Prodigy 10 points

    Hi Carey,

    Thank you for your reply! How easy or hard is it to implement an 8 bit pattern output on the DLP9500 evaluation platform? Is this also the case for the DLP6500 evaluation kit?

    Best regards 

  • +1 in reply to Dominic Mähling
    Intellectual 340 points

    Hi Dominic,

    By design, the DMD is only capable to display a binary pattern at a given moment in time. To project a grayscale image, multiple binary frames have to be time controlled accordingly. Our ALP-4 generates patterns of gray values with the digital precision of FPGA timing. The maximum bit depth is 12 bit; lower resolution can be selected. Using a synchronized detector yields perfect grayscale linearity of 10ppm as it is typically needed in metrology applications of DLP. The grayscale pattern sequence contains the specified number of bit-planes and an efficient algorithm of pulse-width modulation (PWM) is implemented in ALP-4 that results in 260-300 fps (8bit) for various DLP chipsets. The whole grayscale image is subject to the trigger facility so that cameras can be easily synchronized. Flex-PWM is an advanced mode of operation where the user has free control over the bit-plane timing by external trigger.

    We support both the DLP9500 as well as the DLP6500.

    For pricing please contact our DLP Sales Team at dlp@vialux.de

    Best, Phil