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DLPC3437: the way to burn FPGA SPI FLASH

kevin.huang_FJXM
Expert 2925 points
Part Number: DLPC3437

FPGA model: XC7Z020-1CLG484I4493

DDR3 model: MT41K64M16TW-107: J

DLPC model: dlpc3437

According to the 0.33 male board DLPDLCR3310EVM DISPLAY BOARD cable given by TI, the video input of FPGA uses GM8775C to convert MIPI to dual 8-bit LVDS to drive FPGA, leaving out the lowest bit of each group: FPGA_ AP/AN and FPD0_ AP/AN, as shown in the figure below

Like the public version, we also use external SPI,

Please provide the corresponding FPGA software (the way to burn FPGA SPI FLASH)

  • 0
    TI__Genius 12785 points

    Hello User,

    Welcome to the E2E forum and thank you for your interest in DLP® technology!

    The firmware for the DLPDLCR3310EVM can be found on the EVM product page under the DLPDLCR3310EVM FPGA package. This firmware can be flashed through the GUI.

    Kind regards,

    Austin 

  • 0
    Prodigy 30 points

    the video input of FPGA uses GM8775C to convert MIPI to dual 8-bit LVDS to drive FPGA, leaving out the lowest bit of each group: (FPD0_ AP/AN and FPD1_ AP/AN), as shown in the figure before, which is different from the  0.33 male board DLPDLCR3310EVM. Please provide the corresponding FPGA software according to our hardware configuration.

  • 0 in reply to wei gao
    TI__Genius 12785 points

    Hello User,

    Unfortunately we do not have the FPGA source code available for distribution and we cannot support custom builds. We will not be able to fulfill this request.

    Kind regards,

    Austin

  • 0 in reply to Austin Snyder
    Prodigy 30 points

    According to the 0.33 male board DLPDLCR3310EVM， the FPGA is driven by  RGB888（PDATA0-23,H,V,DE,CLK） . If the signal is input through the LVDS channel (dual 8-bit LVDS, leaving out the FPD0 and FPD1_ AP/AN,), will the FPGA automatically detect and switch to this channel under the default software?

  • 0 in reply to wei gao
    TI__Genius 12785 points

    Hello,

    It is highly unlikely that the FPGA will adjust for this, but I will check in with the team to confirm. I should note that many of my colleagues are unavailable during this holiday season. It may be January before I have a reply.

    Regards,

    Austin

  • 0 in reply to wei gao
    TI__Genius 12785 points

    Hello,

    I have spoken with our FPGA team. We will, unfortunately, not be able to meet this request.

    Thank you for your understanding.

    Regards,

    Austin