• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 28 subscribers
  • Views 351 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DLPC1438: Possible discrepancy in the programmer's guide or a misunderstanding?

David O'Brien
Prodigy 40 points
Part Number: DLPC1438
Other Parts Discussed in Thread: DLP300S, DLP301S

In section 3.3.2 3D Print Procedure With FPGA Front-End (Page 33) step 4, the guide states that SPI images are sent into non-active buffer

But, in section 3.3.12 Write Active Buffer (pg 38), it states the following:

1. The active buffer receives the incoming data from the SPI font-end.

2. The inactive buffer contains the data that is actively transmitted to the ASIC.

To me, unless I'm misunderstanding, I'm assuming a system with an FPGA buffer works as follows:

1. Set active buffer to buffer 0.

2. Send an image into buffer 0.

3. Change buffer 1 to active and buffer 0 to inactive. This sends the data from buffer 0 through the parallel lines, to the controller, and then into the memory cells of each micromirror.  

4. When commanded to expose n frames via the external print layer control command, the controller sends a global clocking pulse to the DMD to update all mirror positions.    

  • 0
    Prodigy 40 points

    Attached are a couple of screenshots from the guide

  • 0 in reply to David O'Brien
    TI__Expert 8530 points

    Hi David,

    The wordage is definitely confusing 

    For clarification we can say there are two buffers roles. 

     

    Buffer Role A (actively transmits data to ASIC)

     

    Buffer Role B (receives incoming data from SPI front end)

     

    Buffer 0 and 1 can be configurable for either of these roles so they are interchangeable and multipurpose.

    For efficiency sake we use two buffers so one is performing role A and another is performing role B at the same time. 

    I am trying to confirm more with the team on the exact wordage the descriptions should be and will get back to you as soon as possible.

    Thanks,

    Alex Chan

  • 0 in reply to Alexander Chan
    Prodigy 40 points

    Thanks Alex for the quick response - I'll await your final confirmation but I think that means step 4 d should say the image is placed into the active buffer, not inactive.

    Can you also confirm (or deny) parts 3 & 4 of my understanding?

    Specifically, when a buffer actively transmits to the ASIC, is it sending the data into the memory cells of each micromirror?

    And when the external print layer control command is sent, is a global clocking pulse sent to the DMD?

  • +1 in reply to David O'Brien
    TI__Genius 12785 points

    Hello David,

    We will work on the wording of this section to make it more obvious.

    David O'Brien said:
    Can you also confirm (or deny) parts 3 & 4 of my understanding?

    I would say this procedure is a bit incorrect. I would rewrite to be:

    1. Set active buffer to buffer 0.

    2. Send an image into buffer 1.

    (The inactive buffer receives the SPI image data. However, it is unlikely that you will need to specify which buffer is targeted for the data as only one will be available. The image data would simply be sent over the SPI interface to be received by the available buffer. The important thing to note is that the buffers are swapped after all image data is received.)

    3. Change buffer 1 to active and buffer 0 to inactive. This prepares the data to be sent from buffer 1 through the parallel lines, to the controller. The data is not sent to the controller until the Write Parallel Video (C3h) command is set to 1 - Read and send buffer.  After Write Parallel Video is set for the first layer, it will not be necessary for the following layers.

    (Point 5.a. ("This causes the FPGA to read and transmit the data on buffer 0 while allowing data to be written to buffer 1") may be the point of confusion here. It should say "This causes the FPGA to transmit the data on buffer 1 to the DLPC while allowing data to be written to buffer 0, since buffer 1 is active and buffer 0 is inactive.)

    4. When commanded to expose n frames via the external print layer control command, the controller sends data to be timed with the high speed clock.

    David O'Brien said:
    And when the external print layer control command is sent, is a global clocking pulse sent to the DMD?

    I am not sure what is meant by "global clocking pulse." The pixel data is transmitted from the ASIC to the DMD via the subLVDS D_P(x) and D_N(x) lines as timed by the DCLK_N/P clock lines after the External Print Layer Control Command is sent.

    Please let us know if this clarifies everything or if any question remains.

    Regards,

    Austin

  • 0 in reply to Austin Snyder
    Prodigy 40 points

    Thank you, that greatly clarified my understanding of the buffer system. But my mistake; instead of global clocking pulse, I should have said mirror clocking pulse which is utilizing global mode. I read about this in chapter 4 of publication 1DLPA008B, DMD 101. Are my next two presumptions correct?

    1. The mirror clocking pulse is utilizing global mode

    2. This pulse is part of the sub-LVDS signals?

  • 0 in reply to David O'Brien
    TI__Expert 8530 points

    Hi David,

    Let me look into this and get back to you. Thanks for your patience.

    Thanks,

    Alex Chan

  • +1 in reply to Alexander Chan
    TI__Expert 8530 points

    Hi David,

    The DLPA008B, DMD 101 documentation is for an older architecture and generation so some of the terminology like mirror clocking pulse is not relevant.

    The DMD101 documentation is for 12 degree tilt DMDs while for the DLPC1438 controller, it is paired either with the DLP300s or DLP301s DMDs which use a 17 degree tilt. 

    Thanks,

    Alex Chan