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DLPC410: Dlpc410 float error in my designed PCB

Jack Chen
Prodigy 32 points
Part Number: DLPC410
Other Parts Discussed in Thread: DLPLCRC410EVM, DLPR410B

Hello,

      We have a dlpc410EVM board for our reference from TI,and we designed PCB.On the  dlpc410EVM,the FPGA is Vitex-6,but in our designed board,the FPGA is Kintex-7.

Now there are some errors as follow:

       1.Assert PWR_FLOAT when system is power-up state, DMD will not float, and leave a static image on the DMD.

        2.Assert PWR_FLOAT and then power down,DMD will leave a static image but it will be disappeared after 2-3s.

        3.To restart after assertion of PWR_FLOAT the DLPC410,we assert ARST low then high.But now,DMD will get abnormal.All image display by DMD will get dark.

 But if we power down to restart after assertion of PWR_FLOAT the DLPC410,DMD work normally.

        4.I wonder know that  how long time that ARST low then high.

        Please help me and give some advice,Thanks!

  • 0
    TI__Guru 54705 points

    Hello Jack,

    It is the Easter weekend here in the US.  Sorry for the delay on the response. 

    I am a little confused.  First, the DLPLCRC410EVM board uses two Virtex 5 FPGAs.  One is the LX50 used as the APPS_FPGA which runs code that connects with the GUI.  The other is the Controller (DLPC410) which is configured by the DLPR410 PROM.

    It sounds like your design uses the Kintex-7 as your APPS_FPGA.  Is this correct.  How are you asserting Power Float? 

    Unfortunatly there are two items that use the term Float.  Mirror Float (we are moving to the terminology Float) and Power Float (we are moving to the terminology DMD Park).  It sounds like you are using the DMD Park which requires a restart to work.

    Which version of the DLPR410 are you using?  There is DLPR410 (v5), DLPR410A (v7), and a DLPR410B (v0).  

    Please answer these questions so that we can better assist you.

    Fizix

  • 0 in reply to Fizix
    Prodigy 32 points

    1.Yes,it is correct,my design uses the Kintex-7 as my APPS_FPGA.

    2.I am not sure about the difference between Float and Park.According to the describetion of the dlpc410 datasheet，the operation of Float is asserting the pin named PWR_FLOAT,the operation of Park is by assertion of the proper BLK_MD and BLK_AD.Is that correct? If it is correct,our discussion is about Float not Park.And now, the question is only number 1 and number 2，others has been solved .In my PCB design, there is no difference between TI's design and my design about the Float as shown in the picture below.

    3.DLPR410A (v7) is our using.

  • 0 in reply to Jack Chen
    TI__Guru 54705 points

    Jack,

    Thank you for the information back.  The PWR_FLOAT (This will be the PARK) is a one way ticket, that is it does a specialized mirror reset waveform and then the logic stops running.  Please be sure that there is enough bulk capacitance for the power_down sequence to complete.  This can be found in the DLPC410 data sheet.  Therefore our discussion is about Park and not Float.  

    The circuit you show is for the Power Down operation.

    Section 10.1 Power Down Operation of the data sheet specifies that the bulk capacitance must hold up long enough for 300 us.

    The so called Mirror Float (will be called FLOAT) is recoverable and done by BLK_MD and BLK_AD.  This causes the mirrors to go nominally flat, but normal operation can resume afterward.

    In the current data sheet section 8.4.2.6 DMD Park Mode spells out both operations. 

    Once you use the PWR_FLOAT the data sheet does not specify how long ARSTZ must be asserted to restart the system.  The system will need to go through "training patterns" again.  If your FPGA does not restart the training then it will not initialize correctly.  Your FPGA should be the one to assert ARSTZ to the DLPC410 when the training patterns are up and running.

    Fizix

  • 0 in reply to Fizix
    Prodigy 32 points

    Hello Fizix,

    Thanks for your reply.

    I have understood that what is the Park and Float.The bulk capacitance that our using is the same as TI's design as shown in the picture bellow,the value is 0.1uF. And i have already restarted the system by asserting ARSTZ correctly.Now the biggest question is  when assert PWR_FLOAT when system is power-up state, DMD will not float, and leave a static image on the DMD.And assert PWR_FLOAT and then power down,DMD will leave a static image but it will be disappeared after 2-3s.And i will computer the  hold up time.

  • 0 in reply to Jack Chen
    Prodigy 32 points

    If system power down，the bulk capacitance must hold up long enough for 300 us. But now when system is power_up,assert the "K7_PWR_FLOAT",the bulk capacitance should have no influence for Dark in my understand,but there are still a static image and it will not disappeare unless system power down.

  • 0 in reply to Jack Chen
    TI__Guru 54705 points

    Hello Jack,

    You are correct.  In the case of asserting the DDC_PWR_FLOAT via the K7_PWR_FLOAT, the system does not need to depend on the bulk capacitance.

    To restart, does your K7 start running the training patterns and then assert ARSTZ?  

    Fizix

  • 0 in reply to Fizix
    Prodigy 32 points

    Hello Fizix，

    Yes，i can restart successfully at any position.So could you give me some advice to solve the question about the static image.The most difference between TI‘s design and my design is the power supply，TI’s design is 5v and then boot to 12V. And my design is 12V power supply.

    Jack

  • 0 in reply to Jack Chen
    TI__Guru 54705 points

    Jack,

    The boost from 5 V to 12 V should not cause any issue.  Let me send you a friend invite.

    Fizix

  • 0 in reply to Fizix
    TI__Guru 54705 points

    Jack,

    Per our conversation, please repost this in the China E2E forums so they can better assist you.  Copy the original post and add a link to this post for reference.

    Fizix