Hi TI expert
As the DLPC23x-Q1 ASIC input interface supports a subset of the industry standard OpenLDI (FPD-Link I) interface (Open
LVDS Display Interface Specification v0.95 - May 13, 1999), and in the v0.95 Spec shows , the receiver shall be able to tolerate a minimum of 1 bit time skew between independent differential pairs.
Can you explain how to implement this feature in IC side?
BR Jingcheng
JingCheng,
The DLPC230 does not support dual ports simultaneously and this implementation does not support 1 bit skew for a single port. The DLPC230 was designed and has pins for two ports. See section 5-3 of the datasheet - note 1.
The DLPC230 does support a 1 bit skew between ports. However, to this point we have only implemented systems that support pixel clock up to 110MHz on a single port. Potentially, in the future if we have DMD that needs higher resolution, then may implement and make available dual port configuration and in this case the 1 bit skew between each port would be supported. From a IC input ot the DLPC230, the system should be designed to use a single port that support 24 bit RGB data up to 110MHz. In this case, the maximum skew for a single port is defined as Tskew in section 6.14 of the datasheet. https://www.ti.com/lit/ds/symlink/dlpc230s-q1.pdf. Let me know if this addresses the questions. There are a couple of other open thread that I will address the timing requirements.
Let us know if this addresses your question.
