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DLPC230-Q1: OpenLDI timing

Part Number: DLPC230-Q1
Other Parts Discussed in Thread: SN65DSI83

I am calculating the openLDI timing for DLPC230-Q1, so two questions that:

1. can we consider Tskew in DLPC30-Q1 datasheet(figure1) is Rsposn_min/max (figure2) mentioned in snla249.pdf? 

2. does Tskew include input CLK cycle to cycle jitter? 

thanks a lot!

figure1

figure2

  • Which transmitter part number are you using or considering?  We need to find an expert on the FPDlink team that can help address this question and the others that you have.  The openLDI on the DLPC230/DLPC231 is a hard coded phy which is compatible to the standard, but we do not have detailed expertise on this team on the protocols.  Therefore, I want to move this question to the right team.

  • Which transmitter part number are you using or considering?  We need to find an expert on the FPDlink team that can help address this question and the others that you have.  The openLDI on the DLPC230/DLPC231 is a hard coded phy which is compatible to the standard, but we do not have detailed expertise on this team on the protocols.  Therefore, I want to move this question to the right team.

  • Thanks for the reply, we are considering to use SN65DSI83 as transmitter.

    Our target is to generate the cable CLK to data skew, so we are calculating openLDI timing based on snla249.pdf method, this method use Rsposn, Rsposn definition seems a little different with Tskew of DLPC230-Q1, so want to know how to translate Tskew to Rsposn?

  • In other words, DLPC230-Q1 defined the input data position, not the receiver strobe postion (Rsposn), not strobe window mentioned as snla249.pdf definition, so can we think for DLPC230-Q1 openLDI timing margin = Tskew - Tx output data pulse variation - PCB CLK_to_data skew - ISI - input CLK cycle to cycle jitter? thanks.

  • Wenjun,

    Tskew is similar to RSKM in the app note.  In this case, the max variation must be less than 400ps for every bit in the transmission.  Additionally, the Tjitter Must be considered together with Tskew.  This means that 100ps of jitter must be substracted from the skew.  In the extreme case, if the skew 400ps and the jitter were 100ps, then the DLPC230 would be guaranteed to clock in the data correctly.    Therefore, to guarantee successful operation you would need allow for jitter to substract available skew margin.  

    Let us know if this addresses your questions.

    Thanks,

    Jason

  • Thanks for your quick reply! I have two further questions hope to discuss with you.

    If,

    transmitter data output pulse variation: +/-a

    Clk cycle to cycle jitter: +/-b

    PCB CLk to data skew: +/-c

    Clk jitter due to ISI/crosstalk/reflection: +/-d

    Data jitter due to ISI/crosstalk/reflection: +/-e

     

    So the final margin=Tskew-a-b-c-d-e, is this right? 

    Is it necessary to consider d and e? maybe this is too pessimistic to sum up d and e directly.

    thanks!

  • Hi Wenjun,

    Based on discussion with the HW designers for this function in the DLPC230, we think you have to consider a-b-c-d-e together.  Finally, the max skew allowed is everything together at the input of the DLPC230.    Basically, the +/- 400ps is the total allowed skew at the input of the DLPC230.  Let us know if this make sense.  

    Thanks,
    Jason

  • Hi Jason,

    Thanks for your help! still have several questions want to consult you.

    1.Is tjitter required for cycle to cycle or peak to peak? As they are different meanings for jitter measurement. If it is for cycle to cycle, how this cycle to cycle jitter impact the timing margin for below timing diagram?

    2.Is tip0~6 measured from data P/N cross point to the middle of CLK rising edge?

    thanks

    wenjun

  • Wenjun,

    1. It is cycle to cycle.  If the cycle is short (-100ps) then, it would reduce the margin for a specific clock to data capture.

    2. Basically, yes.  The DLPC230 will detect data transition and change the bit state internally once the transition is detected.

    Jason

  • Hi Jason,

    can we use this equation to calculate the margin? margin = Tskew - a - b -c

    • cycle to cycle jitter: +/-a
    • data position variation related the current cycle CLK rising edge(right???) at receiver: +/-b
    • CLK to data PCB skew: +/-c

    And I am still curious why cycle to cycle jitter should be subtracted from Tskew. As from timing diagram, Tskew is only related with the current cycle CLK rising edge, not related with previous or post cycle CLK rising edge.

    thanks

    wenjun

  • Wenjun,

    Yes this calculation is accurate.  The reason that the cycle to cycle jitter has to be subtracted is that it will reduce period for a given data bit transition and thus reduce the margin for that cycle.

    Jason

  • Hi Jason,

    Thanks for your reply and patience.

    one more question: as below figure, is tip0~6 related with the present cycle clk rising edge or the last cycle clk rising edge ? if it is related with the last cycle clk rising edge, then this makes sense to subtract cycle to cycle jitter.

    datasheet doesn't indicate the tip1 value, it should be equal to tskew, right?

    thanks

    wenjun

  • Wenjun,

    I will need to ask this detail from the HW team to see if they know.  Please wait.

    Jason

  • I sent a note to the HW designer asking for more clarification.

  • Thanks a lot, I will wait for this information.

  • Should have something in a day or two

  • Wenjun,

    Here is direct response from the HW engineer.

    The Tip1 data transition point can be up to + or – 400ps relative to that clock edge (tskew).  Internally, the 7x clock that is clocking the bits out will have jitter, and this has to be within the +/-400ps of the ideal for each bit time, and cumulative jitter across the 7 bit times not to exceed the +/-400ps at the next Lx_CLK rising edge. 

    The requirement is the timing outlined.  Please evaluate internal timing budgets and model for transmission delays and ensure they are meeting the timing spec.  Cycle-to-cycle jitter on the Lx_CLK does impact tip1 (can either increase or decrease the allowed range, i.e. it will shift the tip1 window with the next clock edge).

    Let me know if this addresses the questions.

  • Hi Jason,

    Many many thanks. 

    Want to double confirm if the cause and effect (my understanding) is like below:

    Cause1: As internally the 7x clock that is clocking the bits out will have +/-400ps jitter of the ideal for each bit time,

    Effect1: so this make data transition point Tip1 can be up to +/-400ps relative to that clock edge(tskew).

     

    Cause2:  as cycle to cycle jitter will impact 7x clock to sample the bits,

    Effect2: so cycle to cycle jitter will increase or decrease tip1.

    thanks

    wenjun

  • Hi Wenjan,

    Yes both 1 and 2 is correct understanding.

    Jason

  • Hi Jason,

    sorry, still have one tip0~6 measuring point question want to double confirm with you: 

    is Lx_CLK measured at middle of edge or Vih? Is Lx_data measured at P/N crosspoint or Vih/Vil? If measured at Vih/Vil, what's the value for the Vih/Vil?

    thanks

    wenjun

  • Hi Wenjun,

    Please allow us a couple extra days to look into this.

    Thank you for your patience,
    Michael Ly

  • Wenjun,

    The data and clock are triggered at the crossing point.  There is no "Vih" or "ViL" spec for this type of signal.  The receiver detects the switching point at the input and the signal must be within the spec show in table 6.9.  

    Let us know if this answers your question.

    Thanks,

    Jason

  • Hi Jason,

    it is clear, thanks a lot!

    want to double confirm for VID definition of table 6.9, is VID definition same as IVodI relative to 0V? Or +Vod - (-Vod)=2xVod? as below figure, thanks!

  • Wenjun,

    Yes, I looked at the internal document.  It is basically the same, but the tf adn tr are not defined, so the data eye must be larger than than the minimum VID and the crossover point is the transition.

    Thanks,

    Jason

  • You are welcome.  If all your questions are answered.  Please click the resolved button.  Thanks, Jason.