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DLPC120-Q1: The radiation emission of DMD interface does not meet the requirements

Bruce Yang
Prodigy 180 points
Part Number: DLPC120-Q1

Tool/software:

Hi，During the test of our DLPC120+DLP3030 system, RE did not meet the requirements (AV value of about 76MHz exceeded 3dB). After investigation, it was caused by the clock at the DMD interface. We have done shielding treatment for FPC cbale, but it still did not meet the requirements. In addition, we changed the resistance of DMD-CLK and DMD-SAC-CLK from 20 ohms (EVM resistance value) to 33 ohms and passed the test. However, please help to confirm whether increasing the resistance value has other effects.

  • 0
    TI__Intellectual 2895 points

    For this change, please  verify the signal integrity of the DMD clock and SAC_CLK at the pins of the DMD.  Are the setup and hold times still met correctly?  

    https://www.ti.com/lit/ds/symlink/dlp3030-q1.pdf  - See table 6.7 in the DMD datasheet.  Are the signals still in spec?  Is the voltage level of the signals still in spec?  Also, consider temp and process variation.  If these signals are robust and well within spec, then it is OK.  If not, then perhaps another solution has to be considered.

    Jason