Part Number: DLPC230-Q1
Tool/software:
Hi,
The pixel clock output from the SoC MIPI DSI TX to TI941 is 46.3 MHz. The TI941 generates internal timing parameters HACT=1152, VACT=576, HBP=20, HPW=20, HFP=105, VBP=3, VPW=5, VFP=7, and DLP230 can be displayed. However, when switching to the SoC output the same timing, The DLP230 cannot display.
According to the document "snla132g.pdf", the effective resolution of 1152*576 can be read. When connected to the Tianma screen (model: TM070JDHP08), with the same configuration of SoC and SerDes, the screen can also display normally. Could you please explain what might be the reason for DLP230 not being able to display?
