What's the lifespan of a TI DLP3000 device? When does mirror start locking out?
Does TI have ref design to implement the DLP controller in an FPGA, instead of using DPLC300? Or, FPGA code to drive any TI DLP will help.
Thanks,
John
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello Arrow,
For a good discussion and understanding of DMD lifetime please refer to this thread:
http://e2e.ti.com/support/dlp__mems_micro-electro-mechanical_systems/f/94/t/136635.aspx
Regarding an implementation of the DLP controller into an FPGA, we only support the use of DLP controllers/ASICs for use with DMD's. This is to ensure reliable operation of the DMD mirrors.
Fizix