DDC4100 APPSFPGA OSERDES question

Donald Conkey

Hello,

My question relates to the APPSFPGA reference code,
I'm trying to understand the interface between the appcore module to the DDR OSERDES as I'm programming my own FPGA module.

I can see that the appcore_dout_x_q signals are 64 bits wide which are interleaved to 16 OSERDES cells using
(i,i+16,i+32,i+48) where 'i' is the i'th OSERDES cell.

My appcore design is using clk_g which is 100MHz. I shift in 64 bits of data to the appcore_dout_x_q registers and assert
the appcore_dout_valid right after, for one clk_g cycle.

I was wondering for how many clk_g cycles should the data stay stable in the appcore_dout_x_q register (64bits)
after the data_valid signal was asserted?

Thank you

over 13 years ago

0 Fizix over 13 years ago

TI__Guru 54705 points

Hello Donald,

I will need to speak to one of our FPGA Engineers on this item. I will try to have something back for you in a day or two.

Fizix

0 Donald Conkey over 13 years ago in reply to Fizix

Prodigy 100 points

Thank you.

0 Fizix over 13 years ago in reply to Donald Conkey

TI__Guru 54705 points

Donald,

This is the response from our FPGA team:

The instances of the Xilinx OSERDES primitive provide the output DDR signals. The instance is done in the ddr_lvds_io_ea.vhd file. So it will depend on how your implementation of the Xilinx OSERDES cell is using the inputs.

The Xlinix datasheet and/or simulation should help validate the correct signaling.

I hope this helps.

Fizix.

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DDC4100 APPSFPGA OSERDES question