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About the Input Trigger settings under the pattern sequence mode

Natty Dale
Prodigy 225 points
Other Parts Discussed in Thread: DLPC300

In the dlpu04a documents, there is some hint about the exposure time range, eg. for 8 bit depth the exposure time lists is between 8333us to 20ms Or, for 1bit depth  the minimum trigger period(exposure time) is 250us.

And in your control software, when i set the exposure time higher than maximum value (e.g. 2sec for 1bit, or 20ms for 2bit), the command did failed. While when the exposure time setting is smaller than the minimum value(but not 0), the command success.  My first question is can you tell me what the firmware will do when exposure time setting is smaller than the minimum value?

My second question is for the trigger period and trigger delay, is there any limitations on these two values? It seems no matter how long the trigger period i set, the command always succeeded. While the true period is not what i set to. e.g. the trigger period is set with 10 second, while the light crafter does not output the pattern in 10 seconds period.

  • 0
    TI__Expert 4500 points

    Hi Natty,

    The Exposure time is the number of us the pattern is displayed on the screen while the Trigger Period is the delay between two consecutive patterns. Since there is a slight delay between the trigger received and pattern projected, the trigger period should be always set slightly higher than the Exposure time. Or the GUI automatically adds additional 250us to trigger period.

    1) My first question is can you tell me what the firmware will do when exposure time setting is smaller than the minimum value?

    When the exposure time is set to less than the minimum value, the min. exposure time is added automatically based on the bit depth. The GUI allows a min exposure time of 'zero' only for 1-bit depth patterns.

    2)My second question is for the trigger period and trigger delay, is there any limitations on these two values?

    The minimum trigger period is 250 us, since the FPGA needs a load time of 250 us to upload patterns in to the mddr (mobile circular buffer). The trigger delay can be set as shown in the timing diagram above.

    3) It seems no matter how long the trigger period i set, the command always succeeded. While the true period is not what i set to. e.g. the trigger period is set with 10 second, while the light crafter does not output the pattern in 10 seconds period.

    In reality, when you set a trigger period of 10 us, the actual trigger period changes to (10+250) us.


    Hope this helps!

    Regards,

    Divya

  • 0 in reply to Divya Reddy
    Prodigy 225 points

    Hi Divya, thanks.

    【the trigger period should be always set slightly higher than the Exposure time. 】 - is there any exact value to define the slightly higher? 

  • 0 in reply to Natty Dale
    TI__Expert 4500 points

    Hi Natty,

    As I mentioned above, it is the pattern load time to FPGA (250 us).

    Regards,

    Divya

  • 0 in reply to Divya Reddy
    Intellectual 300 points

    Just to clarify, the trigger settings we talk about here is not the same as the "output trigger" for external cameras, correct?

    I'm working on a FPGA design. What signals and how do I command DLPC to trigger the internally stored patterns? I'm reading DLPA042. Figure 3 seems to illustrate what I want, but no specific timing requirement.

    Does the FPGA still rotates the buffer? If FPGA didn't rotate the buffer, what will happen? How to control pattern loopback/play once?

    What is the proper setting for DLPC registers for internal stored patterns:

    • Video Frame Rate control (0x19)
    • Input source selection (0x0B)
    • Sequence Sync Mode (0x1E) - free-run or Lock-to-VSYNC

    Thanks,

  • 0 in reply to William Wang91
    TI__Mastermind 30875 points
    Does the FPGA still rotates the buffer? If FPGA didn't rotate the buffer, what will happen? How to control pattern loopback/play once?
    [Sanjeev] FPGA configured to generate sync (vsync with 2-lines) that will basically cause DLPC300 to jump to next buffer. Note, buffer rotate request is first coming from DLPC300 only then FPGA is generating the syncs to jump to next buffer. If FPGA is not generating the sync, DLPC300 continue to display from the same buffer.

    LoopBack - FPGA should continue generating syncs all the time until stop
    PlayOnce - The SYNCs are generated pre-defined number of times.

    Regards,
    Sanjeev
  • 0 in reply to Sanjeev
    Intellectual 300 points

    "If FPGA is not generating the sync, DLPC300 continue to display from the same buffer. "

    1. Let's say there are multiple patterns in the same buffer, does DLPC300 loops back to the first pattern automatically if no VSYNC comes when BUF_SWAP asserts?

    2. Assuming no VSYNC is sent, so it never rotate to the next frame buffer. How to stop it from looping through the patterns in the same frame buffer?

    3. Is the only way to control pattern exposure time through the sequence vector setting (eg. Table 2-113)? 

    4. It seems like LightCrafter software offer pattern playback control through software/external trig (display one pattern until an async. pattern trigger comes)? How is this achieved? We want to design our FPGA to do the same.

    Thanks!

  • 0 in reply to William Wang91
    TI__Mastermind 30875 points
    #1. No. Each pattern in buffer is displayed only on the vsync; whenever the BUF_SWAP the FPGA will generate the pusedo sync logic vsync + 2 h lines to cause DLPC300 to switch to next buffer and start displaying.

    #2. Sending No VSYNC itself is like stopping. Pattern display will not be advanced until vsync. Suppose there are say, 5 patterns in the buffer to be displayed, after 3rd pattern, if no vsync is coming, then it will continue to show the current data; but the LED enable and exposure signal go low, so camera will not be able to see the pattern; even if the pattern data continue be shown on the DMD.

    #3. Yes.

    #4. This part is controlled via logic in FPGA.

    You can have [Your FPGA] => [TI FPGA + DLPC300] you can configure TI FPGA and DLPC300 via I2C interface.

    Regards,
    Sanjeev