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DLPC200 power-on sequence

Other Parts Discussed in Thread: DLPC200, DLP5500

Hi

according to the datasheet , DLPC200 should have a right power-on sequence


in the designing of my own  DLP board ,
how can i control it ? and how can i check it ?

Thank you !

-diaoxiaochun

  • Hi Diao,

    The DLPC200 power on sequence is documented in DLPC200 controller datasheet http://www.ti.com/lit/ds/symlink/dlpc200.pdf and DLP5500 chipset specification http://www.ti.com/lit/er/dlpz004b/dlpz004b.pdf.

    If you are designing your own board then you must consider following important points:

    1. DLPC200 (http://www.ti.com/lit/ds/symlink/dlpc200.pdf) ensure the 50MHz clock meets the speicification provided under Table 5. Reference Clock Oscillator Requirements

    2. The core supply voltages to DLPC200 chip, 1.2, 1.8, 2.5 and 3.3 must be stable and within the range specified under Table 6. Supply Voltages and Minimum Values.

    3. As explained in above point #1, 3.3V must be stable for 2 seconds before global reset occur. PWR_GOOD occurs within 20mSec (this is as per TI Reference design).

    4. Now refer to http://www.ti.com/lit/er/dlpz004b/dlpz004b.pdf, Table 5.5.1, verify all the core voltages are stable and within specification, then only RESET signal must be de-asserted. PWR_GOOD signal can be asserted after that per TI reference design this occurs within 20mSec.

    Regards,

    Sanjeev

  • Sanjeev,

    I have tried to cross-reference your point #3 to the LightCommander schematic. I do not see any 2 second timing and everything controlling the global reset signal is hardware circuits. In the LightCommander, 1.2V, 1.8V, 2.5V, 3.3V, and 12V are all monitored and so is CFG_done. When all rails are high and CFG_done is high, the global reset signal is wired in hardware to go high within 20 msec, and if any of these monitored signals go low, global reset goes low instantly. Can you explain the guidance on point #3 in a way that's consistent with what the LightCommander is doing?

    Thanks,
    Arthur