Differential Pair Length Matching

Erik Morness1

Other Parts Discussed in Thread: DLP7000, DLPC410

Hello,

I have a couple question regarding the differential pair length matching requirements for the 0.7 XGA DLP chipset. Both questions are regarding the differential pair length matching between the DLPC410 and DLP7000 devices.

Are there any length matching requirements between the A & B data busses? if so, what are they?

What are the length matching requirements within the A or B bus?

Thank you and Regards,

Erik Morness

over 12 years ago

0 Divya Reddy over 12 years ago

TI__Expert 4500 points

Hello Erik,

Welcome to TI E2E Community!

The inter-bus matching in A and B are same as intra-bus matching in A or B. Same with C and D data buses.

A,B relative to C,D can be up to 1/4 clock delay.

Regards,

Divya

0 Erik Morness1 over 12 years ago in reply to Divya Reddy

Prodigy 20 points

Hello Divya, thank you for replying.

Can you clarify what you mean by:

Divya said:
The inter-bus matching in A and B are same as intra-bus matching in A or B

Is there a specification for what the length matching should be?

Thank you and Regards,

Erik

0 Fizix over 12 years ago in reply to Erik Morness1

TI__Guru 54500 points

Hello Erik,

This means that you can treat A & B as a single bus so that matching between signals between bus A & B are the same as matching inside bus A and inside bus B.

For layout guidlines you should contact one of our Design House Partners here:

http://www.ti.com/lsds/ti/analog/dlp/solutions-services.page

If you do not already have access to the DLP^® Catalog Extranet, please request access through one of the Design Houses above, it has many extra resources for the DLPC410 based chipsets that are not available on the public website.

Fizix

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Differential Pair Length Matching