Hi,
Right now we make our own DLP control board & DMD FPC, but:
original DLP control board + our FPC: image stable
our DLP control board + original FPC : image stable
our DLP control board + our FPC: image NOT stable :(
our FPC's length is about 5cm, a little longer than original FPC (total length is longer than design constraint )
So, i want to reduce the FPC clock rate from 120M to 80M.
The "dlps029a.pdf" says i can (Table 13. DMD Interface Timing Requirements)
but i cant find out the configuration register in "dlpu010b.pdf"
So my question is how to change the DMD FPC clock rate? or any binary code update?
We need 5cm+ FPC for our design.
Thank You!
Daniel