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DLPC350 PWRGOOD and POSENCE spec

RY9983
Guru 10570 points
Other Parts Discussed in Thread: DLPC350, DLP4500

Hello,

I am reading the datasheet "System Power and Reset" of DLPC350. (dlps029c: P43)
I have a confirmation about relationship between PWRGOOD and POSENSE.
Which is correct spec on power up sequence?

a) PWRGOOD must be high after more than 60msec after rising edge of POSENSE.

b) PWRGOOD must be high after rising edge of POSENSE.
There is no timing spec, but it has effect after more than 60msec.

c) You can PWRGOOD become high before rising edge of POSENSE.
But it has effect after more than 60msec after rising edge of POSENSE.

Best regards, RY

dlps029c:P43 System Power and Reset

  • 0
    TI__Mastermind 30875 points

    Hello RY,

    PWRGOOD is a critical signal for DMD operation reliably.

    With respect to your specific question, what it means is that after the POSENSE goes high, the DLPC350 controller will not take any action or interpret PWRGOOD  signal, if you read the section in PG 43, 100ms for PLL signal stabilize then proceed with DLPC350 controller software boot sequence. 

    The master PLL (PLLM) is released from reset upon the low-to-high transition of POSENSE, but the DLPC350 controller keeps the rest of the controller in reset for an additional 100 ms to allow the PLL to lock and stabilize its outputs. After this 100-ms delay, internal resets are de-asserted causing the microprocessor to begin its boot-up routine.

    #b is correct. PWRGOOD must become high after the rising edge of POSENSE.

    Note, there is a strict requirement, about power-down though, PWRGOOD signal must go LOW atleast 500us before the POSENSE goes low, this will ensure the DLPC350 power-down DLP4500 safely in PARK state.

    Regards,

    Sanjeev