DMD LVDS interface

Hello Kuch,

SCTRL is special interface where instructions from Controller to DMD is flowing. Unfortunately it is an IP, it is not possible to provide any information regarding the same.

Note these signals generated in the TI controller in this case DLPC900, the front-end user is not expected drive theses signals. If you don't mind can you please let us know how you were planning to drive these signals? Like are you planning to use DLP6500 without DLPC900?

Regards,
Sanjeev

Hello Sanjeev.
Yes, I want to use DLP6500 without DLPC900.
Regards,
Kuch

Hello Kuch,
Unfortunately it is not possible to drive DLP6500 directly. We highly recommend driving with DLPC900. Is there anything that is preventing not using DLPC900?
Regards,

Hello Kuch,
I would like to add to Sanjeev's response to emphasize the importance of using the DLPC900. It is a requirement for use with the DLP6500 for reliable functionality and operation.
Thanks,Eric

Hello Sanjeev,

Hello Eric.

What do you mean impossible?The projector uses the chip 4422, and it's not DLPC900. I believe that if I know how to control the chip, it is possible..
If the information is closed, so you can write about it.

I'll tell you why this is necessary.
1 I do not have RGB image. There are only 2 colors. Green and yellow. And I consider it one color.
2. The frequency of change pictures must be a multiple of 8 or 16kHz. Otherwise, a very large energy losses occur.
I think (do not know) that DLPC900 can not perform it. I need to try it without DLPC900.. And I have no DLPC900.

Regards,
Kuch

Hello Kuch,

Thank you for explaining your situation.  Please understand, Sanjeev simply stated it is not possible because TI does not provide a way to drive the DLP6500 without the DLPC900.  I added that it is a requirement from TI's point of view for reliable functionality and operation.

If we determine a solution using the DLPC900 we will let you know. 

Regards,

Eric

Hello Eric,

I realized that the information on the chip DLP6500 I do not get.
I'll wait if you can decide how to manage using an IC DLPC 900.

Regards,

Kuch

Hello Eric,

1. The document DLPS053 -OCTOBER 2014 (DLP6500) p.11 written "VCCI Supply voltage for LVDS receivers 3.3V".
2. The document DLPS037 -OCTOBER 2014 (DLPC900) p.4 written "1.8-V LVDS (DMD interface)".
  Do I need converters for connection of these chips?

Regards,

Kuch

Hello Kuch,
You should not need any converters for the connection of the chips. We will review the documentation to see if this is correct or is an error. Please allow some extra time for responses during the Holiday season here in the United States.
Fizix

Hello Fizix,
where you can see how to work with DMD interface DLP6500FYE ?
And where you can see how to work with the Block Operations DLP6500FYE?
and that has been described as though DLPS024B for DLPC410.
Regards,

Kuch

Hello Trevor,
I would like to receive information about the block mode chip DLP6500FYE.
I'm interested in this question e2e.ti.com/.../386683 . I think the time has passed and there was information on the subject. I'm interested in the signals DATA BUS A(B), SERIAL CONTROL, MICROMIRROR RESET CONTROL.
I would like to make it a description of how to do it in the document dlpc410 dlps024b.pdf , page 24-34, Table 5. DLP9500 2XLVDS DMD Data Pixel Mapping, Table 6. DLP7000 2XLVDS DMD Data Pixel Mapping, and especially Table 7. Block Operations.

Best regards,

Kuch

Hello , Trevor

I've been playing a copper laser images.  His pulse frequency of 8-16 kHz.

I want to synchronize the pulse rate and frame pictures. If this is not done then we have great power loss.

So I want from my device control chip dlp6500.

Therefore, I'm interested in the interface signals dlp6500. And I was particularly interested in block mode.

And I would be very grateful for any information on this subject.

Best regards,
Kuch

Hello , Trevor
Thank you, I've read. And I had questions.
I want to get a picture with a frequency change 8-16kHz. Sense of synchronization signals of the laser and the DMD is to eliminate the possibility of switching the mirrors during a light pulse.
This can be done using a block mode. Image recording unit can be 4 or 15 (16) blocks.
Let this be a Quad Block Mode. Since changes in the Frame (or block) with a frequency 16 kHz can only be true.
On chip DMD should be transmitted by LVDS 4 data block (1-4,5-8,9-12,13-15/16) and 4 reset block( RESET_ADDR, RESET_MODE,RESET_SEL,RESET_STROBE) with a repetition period of T=288 * 30 * 2.5ns. (400MHz).
I have to set the parameters Start block=0 , Number of blocks=0x04 ( DLPU018A, Table 50. DMD Block Load Command Definition).
1. I do not understand that there is a Trigger output Raising Edge delay and Trigger output Falling Edge delay. From what point these delays are counted?
2. I do not know the location of the signal Trigger Out1, Trigger Out2 and Trigger In1,Trigger In2 relative to 4 signals reset block in Quad Block Mode or one reset block in Global mode, ie, in relation to the time of changing the position of the mirrors. Constant position of the mirrors shows Trigger In1 or Trigger Out1? Is it true that the period of these signals is equal to one frame for both modes Quad block mode and Global mode?
3. Raising Edge Trigger In1 - Trigger output Raising Edge delay - Raising Edge Trigger Out1 - it's right?
4. What is the minimum possible time for a pulse and a pause signal Trigger Out1, TRIG_IN1?
5. Is Raising Edge Trigger In1 appear before the falling edge Trigger Out1?
Interval Trigger output Raising Edge delay(>100) + Trigger Out1(>20 ) have more 120mks. How can I get a Dedicated DLPC900 Controller for high-speed pattern rates of 9500 Hz (1-Bit Binar) (105mks )?

I would be very grateful if you would have got to the description of the sequence of signals to reset block for DMD (RESET_ADDR, RESET_MODE, RESET_SEL, RESET_STROBE).

Best regards,
Kuch