Hi,
Instead of using external crystal or oscillator, we want to use the FPGA to generate the input clock for DLPC300. The RESET is controlled by FPGA as well.
Due to limitation of the PLL, we cannot generate 16.667Mhz, but the closest is 16.384Mhz. From DLPC300 datasheet, there is an internal PLL to generate other clocks from the 16.667Mhz input. I'm curious if there will be any timing implications with a slightly reduced input clock?
I understand the RESET should be released after input clock and power rails are stable. Is there any delay requirements between them?
Thank you,
William