I didn't find this in datasheet. Can someone tell me the pin status (high, low, high-z?) when DLPC300 is in reset? I'm particularly interested about the SPI interface pins (clk, din, dout, cs_b).
We are trying to design so the NOR FLASH is programmed by a FPGA during prodcut test. Then during normal startup, the DLPC will load config data from the flash. In other words, we have two masters, but not concurrently. What is your opinion of the following three?
Also, I want to confirm what opcodes are being used by DLPC300 in communication to the SPI flash. The datasheet only says "no normal read", only "fast read". Is there any case where the DIN or DOUT switch IO direction?
Thanks,
William
