transmit timing sequence

1. VSync is actual reference.

2. Yes, you should send or write like any other standard digital video signal on RGB parallel port, so Data 0-23, VSYNC, HSYNC, DATA_ENABLE, PIXEL CLOCK, and frequency  anything upto 120Hz. The important parameter is that the total time needed to display pattern per video frame is < the total video frequency. For example - Input video frequency is 60Hz i.e., 912x1140@60Hz then you chose to displa Pattern P1, P2,...PN, the total display time P1 + P2 + .. + PN must be < 16.67ms.

3.

Refer Section 6.11 Video Timing Input Blanking Specification DLPC350 datasheet  http://www.ti.com/lit/ds/symlink/dlpc350.pdf 

Regards,

Sanjeev

Thank Sanjeev
Thank you for your prompt reply, I am a bit puzzled
1. I use sequence mode, not with the video mode. You give the third point above (Refer Section 6.11 Video Timing Input Blanking Specification DLPC350 datasheet www.ti.com/.../dlpc350.pdf

) The timing, I can understand that you are based on Figure 7. Horizontal and Vertical Blanking Diagram own definition of it? Because I did not find in DLPC350 datasheet. My question is this timing sequence diagram can be used to model?
Timing 2. The trig 0 mode timing chart and DLPC350 Programming Guide on how to understand?

Thank Sanjeev,
I then re-sound at my question, you reply to points 1 and 2. I have reason. I most want to know is if I use FPGA generate the sequence, RGB24 interface transfer DLPC350 by using sequential patterns trigger 0. more detailed timing diagram so what? You can give a similar talk of your "Figure 12. Parallel I / F Frame Timing" The Timing Diagram?
I hope you give an answer as soon as possible.

Regards

Hi,

Your FPGA don't need to perform extra things, it can generate proper video timing like any other monitor device. The key is the resolution and minimum blanking timing requirements.

Part - 1: Generate 912x1140 given frame rate (upto 120Hz), for RGB Parallel Signal timing we have provided you the Figure 12 for reference.

Part -2: Configure LightCrafter 4500 in Trigger Mode - 0, here you have flexibility to choose bit(s) from incoming 24-bit  frame data, so you can select any combination of pattern(s) bit-depth color with one requirement is that the SUM of total patterns selected from display is LESS THAN the incoming video frame rate. For example - Incoming video rate is 60Hz, so available time 16.67ms, so if you chose pattern 1, pattern 2,.... pattern N, so sum of (Pattern 1, Pattern 2 , ... Pattern N) < 16.67ms.

Further as explained in DLPC350 programmer's Guide, Figure 2-9, Trigger Mode - 0 timing example, Sum of  P1 + P2 + [P1 P2 P3] + P4 < FRAME TIME, we have not given exact timing because pattern exposure is user selectable, Similarly, Trig_Out_1 and Trig_Out_2 behavior and signal delay timings are user selectable. 

Let me know if it helps.

Regards,

Sanjeev

Thank Sanjeev, Thank you for your reply.

Finally, I confirm that:

if I just generate 912 * 1140 sequence of pictures with FPGA, you can program the timing you provide transport it?

If that DLPC350 how allocation? Is not serialized transmission mode can not set the trigger model?

Regards

I do not synchronize the camera with a sequence mode, I want to generate a vertical bar type 912 * 1140 images using FPGA, see the character pattern in Fig. Transfer to DLPC350. Show a pattern corresponding to a pixel bars. I do not need the way pictures stored in the internal flash inside

 

Now what I did,
Configure DLPC350 sequence mode, using trigger 0 (these configurations exactly as DLPC350 Programming Manual "4.2 Trigger Mode 0 Example", Set pattern display mode to external video, Set the pattern trigger mode to vsync, etc.). External FPGA generate 912 * 1140 image sequences and RGB port transmission DLPC350 by giving DLPC350.
My question is this:
   1. I do now, according to the timing provided by your FPGA programming, right or wrong my way? .
   2. Could it provide a program that I can serve as a reference (912 * 1140 series transmission program)?
3.DLPC350 Programming Manual "4.2 Trigger Mode 0 Example" is the final step "10. Start the pattern sequence, either with TRIG_IN_2 or 0x1A24." Should be wrong, right? TRIG_IN_2 Should be vsync?

I want to know the answer as soon as possible.

Regards

I do not synchronize the camera with a sequence mode, I want to generate a vertical bar type 912 * 1140 images using FPGA, see the character pattern in Fig. Transfer to DLPC350. Show a pattern corresponding to a pixel bars. I do not need the way pictures stored in the internal flash inside



Now what I did,
Configure DLPC350 sequence mode, using trigger 0 (these configurations exactly as DLPC350 Programming Manual "4.2 Trigger Mode 0 Example", Set pattern display mode to external video, Set the pattern trigger mode to vsync, etc.). External FPGA generate 912 * 1140 image sequences and RGB port transmission DLPC350 by giving DLPC350.
My question is this:
1. I do now, according to the timing provided by your FPGA programming, right or wrong my way? .
2. Could it provide a program that I can serve as a reference (912 * 1140 series transmission program)?
3.DLPC350 Programming Manual "4.2 Trigger Mode 0 Example" is the final step "10. Start the pattern sequence, either with TRIG_IN_2 or 0x1A24." Should be wrong, right? TRIG_IN_2 Should be vsync?

I want to know the answer as soon as possible.

Regards

I do not synchronize the camera with a sequence mode, I want to generate a vertical bar type 912 * 1140 images using FPGA, see the character pattern in Fig. Transfer to DLPC350. Show a pattern corresponding to a pixel bars. I do not need the way pictures stored in the internal flash inside

Now what I did,

Configure DLPC350 sequence mode, using trigger 0 (these configurations exactly as DLPC350 Programming Manual "4.2 Trigger Mode 0 Example", Set pattern display mode to external video, Set the pattern trigger mode to vsync, etc.). External FPGA generate 912 * 1140 image sequences and RGB port transmission DLPC350 by giving DLPC350.

My question is this:

  1. I do now, according to the timing provided by your FPGA programming, right or wrong my way? .

  2. Could it provide a program that I can serve as a reference (912 * 1140 series transmission program)?

3.DLPC350 Programming Manual "4.2 Trigger Mode 0 Example" is the final step "10. Start the pattern sequence, either with TRIG_IN_2 or 0x1A24." Should be wrong, right? TRIG_IN_2 Should be vsync?

I want to know the answer as soon as possible.

Regards

I do not synchronize the camera with a sequence mode, I want to generate a vertical bar type 912 * 1140 images using FPGA, . Transfer to DLPC350. Show a pattern corresponding to a pixel bars. I do not need the way pictures stored in the internal flash inside

Now what I did,

Configure DLPC350 sequence mode, using trigger 0 (these configurations exactly as DLPC350 Programming Manual "4.2 Trigger Mode 0 Example", Set pattern display mode to external video, Set the pattern trigger mode to vsync, etc.). External FPGA generate 912 * 1140 image sequences and RGB port transmission DLPC350 by giving DLPC350.

My question is this:

  1. I do now, according to the timing provided by your FPGA programming, right or wrong my way? .

  2. Could it provide a program that I can serve as a reference (912 * 1140 series transmission program)?

3.DLPC350 Programming Manual "4.2 Trigger Mode 0 Example" is the final step "10. Start the pattern sequence, either with TRIG_IN_2 or 0x1A24." Should be wrong, right? TRIG_IN_2 Should be vsync?

I want to know the answer as soon as possible.

Regards

1).I do not synchronize the camera with a sequence mode,
2)I want to generate a vertical bar type 912 * 1140 images using FPGA, see the character pattern in Fig. Transfer to DLPC350. Show a pattern corresponding to a pixel bars.
3)I do not need the way pictures stored in the internal flash inside.
Now what I did,
Configure DLPC350 sequence mode, using trigger 0 (these configurations exactly as DLPC350 Programming Manual "4.2 Trigger Mode 0 Example", Set pattern display mode to external video, Set the pattern trigger mode to vsync, etc.). External FPGA generate 912 * 1140 image sequences and RGB port transmission DLPC350 by giving DLPC350.
My question is this:
1. I do now, according to the timing provided by your FPGA programming, right or wrong my way? .
2. Could it provide a program that I can serve as a reference (912 * 1140 series transmission program)?
3.DLPC350 Programming Manual "4.2 Trigger Mode 0 Example" is the final step "10. Start the pattern sequence, either with TRIG_IN_2 or 0x1A24." Should be wrong, right? TRIG_IN_2 Should be vsync?

I want to know the answer as soon as possible.

Regards

I do not synchronize the camera with a sequence mode
I want to generate a vertical bar type 912 * 1140 images using FPGA, see the character pattern in Fig. Transfer to DLPC350. Show a pattern corresponding to a pixel bars.
I do not need the way pictures stored in the internal flash inside.
Now what I did,
Configure DLPC350 sequence mode, using trigger 0 (these configurations exactly as DLPC350 Programming Manual "4.2 Trigger Mode 0 Example", Set pattern display mode to external video, Set the pattern trigger mode to vsync, etc.). External FPGA generate 912 * 1140 image sequences and RGB port transmission DLPC350 by giving DLPC350.
My question is this:
1. I do now, according to the timing provided by your FPGA programming, right or wrong my way? .
2. Could it provide a program that I can serve as a reference (912 * 1140 series transmission program)?
3.DLPC350 Programming Manual "4.2 Trigger Mode 0 Example" is the final step "10. Start the pattern sequence, either with TRIG_IN_2 or 0x1A24." Should be wrong, right? TRIG_IN_2 Should be vsync?

I want to know the answer as soon as possible.

Regards

DLPC350 Programming Manual "2.4.3.2 Trigger Controls
To synchronize a camera with the displayed patterns, the DLPC350 supports three trigger modes: "
If not synchronize external cameras or sensors, but using an external FPGA 912 * 1140 resolution transmission sequences may also need to use to trigger it? With variable exposure mode for it?

This is a forum not reviewed articles, I again made step by forgive me.
I do not synchronize the camera with a sequence mode,
I want to generate a vertical bar type 912 * 1140 images using FPGA, see the character pattern in Fig. Transfer to DLPC350. Show a pattern corresponding to a pixel bars.
I do not need the way pictures stored in the internal flash inside

Now what I did,
Configure DLPC350 sequence mode, using trigger 0 (these configurations exactly as DLPC350 Programming Manual "4.2 Trigger Mode 0 Example", Set pattern display mode to external video, Set the pattern trigger mode to vsync, etc.). External FPGA generate 912 * 1140 image sequences and RGB port transmission DLPC350 by giving DLPC350.
My question is this:
1. I do now, according to the timing provided by your FPGA programming, right or wrong my way? .
2. Could it provide a program that I can serve as a reference (912 * 1140 series transmission program)?
3.DLPC350 Programming Manual "4.2 Trigger Mode 0 Example" is the final step "10. Start the pattern sequence, either with TRIG_IN_2 or 0x1A24." Should be wrong, right? TRIG_IN_2 Should be vsync?
I want to know the answer as soon as possible.
Regards

Now what I did,
Configure DLPC350 sequence mode, using trigger 0 (these configurations exactly as DLPC350 Programming Manual "4.2 Trigger Mode 0 Example", Set pattern display mode to external video, Set the pattern trigger mode to vsync, etc.). External FPGA generate 912 * 1140 image sequences and RGB port transmission DLPC350 by giving DLPC350.
My question is this:
1. I do now, according to the timing provided by your FPGA programming, right or wrong my way? .
2. Could it provide a program that I can serve as a reference (912 * 1140 series transmission program)?
3.DLPC350 Programming Manual "4.2 Trigger Mode 0 Example" is the final step "10. Start the pattern sequence, either with TRIG_IN_2 or 0x1A24." Should be wrong, right? TRIG_IN_2 Should be vsync?

I want to know the answer as soon as possible.

Regards

I'm very sorry, only to find many duplicate labels, I get a long time can not be deleted, I'm sorry! In order not to affect the reading. Please help me to delete duplicate posted it! THX

Configure DLPC350 sequence mode, using trigger 0 (these configurations exactly as DLPC350 Programming Manual "4.2 Trigger Mode 0 Example", Set pattern display mode to external video, Set the pattern trigger mode to vsync, etc.). External FPGA generate 912 * 1140 image sequences and RGB port transmission DLPC350 by giving DLPC350.
My question is this:
1. I do now, according to the timing provided by your FPGA programming, right or wrong my way? .

[Sanjeev] We are not able to understand your query exactly. The FPGA should generate the 912x1140 video signals as specified in the data sheet.

The video signal for example 60Hz should as follows
Pixel Clock : 83.6 MHz
Horizontal:
Active Time : 912 Pixels
Blanking Time : 280 Pixels
Sync Offset : 40 Pixels
Sync Pulse Width: 64 Pixels
Border : 0 Pixels
Frequency : 70 kHz
Vertical:
Active Time : 1140 Lines
Blanking Time : 30 Lines
Sync Offset : 10 Lines
Sync Pulse Width: 6 Lines
Border : 0 Lines

Digital Separate, Horizontal Polarity (+), Vertical Polarity (+)


2. Could it provide a program that I can serve as a reference (912 * 1140 series transmission program)?

[Sanjeev] Once you are able to generate the signal on FPGA you can then refer to GUI and EVM user's guide to configure it in pattern display mode.

3.DLPC350 Programming Manual "4.2 Trigger Mode 0 Example" is the final step "10. Start the pattern sequence, either with TRIG_IN_2 or 0x1A24." Should be wrong, right? TRIG_IN_2 Should be vsync?
[Sanjeev] The TRIG_IN_2 is not applicable in Trigger Mode - 0, it should be VSYNC, we will correct the documentation.

Regards,
SAnjeev