EMI issues on DPP6401 solution

Hi Jack-sun,
The 720MHz appears to be a multiple of the DMD Data Clock, 120MHz (6x 120MHz = 720MHz).
Although I am a little surprised that the peak at 720MHz is higher than at 240 & 480MHz. So there may be some other effect or cause going on too.
Have you tried changing the input pixel clock rate to see if that has any effect?
The primary way to reduce the EMI from the electronics is to enclose it in a metal or metalized-plastic enclosure. This would give the biggest attenuation of any EMI for the whole product.
There are other methods of reducing the EMI from the DMD clock:
1) Route the DMD_DCLK and all of the date lines on internal layers of the board, between ground planes. Use as few vias as possible to avoid points at which the signal can radiate.
2) Any connectors or flex cables can also allow significant signal radiation if not designed correctly.
For any flex cables, use a ground plane. Also use a metalized overcoat (e.g. silver epoxy layer) or sheath to reduce EMI.
3) You can also use a different DMD clock frequency (206MHz) which will shift the frequency peaks. NOTE: This would also require use of different sequences specifically designed for this clock frequency. It may just shift the peaks and not reduce them any.
4) Any metal or metalized covers, coatings, sheaths, etc., should be well grounded to help reduce any signal radiation.
Regards,Roger