• State Answer Suggested
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 1084 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DLP4100 programming with TI code sample

Thomas Leclercq
Prodigy 20 points
Other Parts Discussed in Thread: ALP, DLPC410

Hello,

I am working with the DLP Discovery 4100 Board (VX4100 Board) with 0.7 XGA VIS DMD Chip and ALP-4.1 High-Speed Controller Suite extension.

I try to display a pattern on my DMD and for that I use the example code provided by TI (VHDL). I understand it a little but there are still some incomprehensible. I understand the pattern is generated into PGEN entity but when I want to adapt it doesn't work as I wanted. For instance, when I fix the pattern1 and pattern2 signals values, I have a black screen on my DMD and I don't understand the reason for that. So with this one, how can I adapt the PGEN's architecture to create my own pattern ?

Thank you

Best regards,

  • 0
    Prodigy 190 points
    Hello Thomas,

    The easiest way to display a pattern should be just using the ALP software. ALP basic GUI, for example can load image files and display them on DMD. ALP-4.1 high-speed adds sequences and real-time behaviour.

    However, if you really need to do the VHDL work, then please first make sure that you can build the FPGA design from unmodified example code. Does it work as expected? Then you can adjust the PGEN signals. Please also note that the example code uses the DIP switch inputs.

    Hope that helps, Best Regards
    Frank
  • 0 in reply to Frank L
    Prodigy 20 points

    Hello Frank L

    Thank you for your answer. I have to drive my DMD with an FPGA so I must make the VHDL code work. If I build the example code without modifications it works but when I change PGEN output signal it doesn't work as expected, it sometimes display something that change when I change the reset mode. It's strange.

  • 0 in reply to Thomas Leclercq
    Prodigy 190 points
    Hello Thomas,

    Than you should check it in a VHDL simulator.

    The counter cnts_pattern_cnt_q is a primary input for pattern generation. It affects intermediate signals like pgen_row, pattern, pattern1/2.... And finally the DLPC410 control signals (especially DVALID, ROW_MD/AD) must match the data signals douta/b/c/d.

    So changing pattern1/2 might affect data, but at the wrong time.
    I think you will faster see your changes when you keep pattern1/2 as it is, and instead change the literals that are assigned to douta/b/c/d_temp1/2.

    Best Regards
    Frank