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DLPA3005 datasheet questions

Rossinag
Expert 1705 points
Other Parts Discussed in Thread: DLPA3005

Dear All,

Please let me ask DLPA3005 questions.

1) 7.3.2.5.1 Power Good

Both the Illumination driver and the Illumination LDO have a power good indication. The power good for the driver indicates if the output voltage (VLED) is within a defined window indicating that the LED current has reached the set point. If for some reason the LED current cannot be controlled to the intended value, this fault occurs. Subsequently, bit ILLUM_BC1_PG_FAULT in register 0x27 is set high. The illumination LDO output voltage is also monitored. When the power good of the LDO is asserted it implies that the LDO voltage is below a pre-defined minimum of 80% (rising) or 60% (falling) edge. The power good indication for the LDO is in register 0x27 (V5V5_LDO_ILLUM_PG_FAULT).

Question) We would like to know the "defind window" of VLED. Is this the VLED_ANODE? If so would you please explain meaning  of  the "0.85x" of min value?

2) 7.3.2.5.2 Ratio Metric Overvoltage Protection

The DLPA3005 illumination driver LED outputs are protected against open circuit use. In case no LED is connected and the PAD device is instructed to set the LED current to a specific level, the LED voltage (ILLUM_A_FB) will quickly rise and potentially rail to VIN. This should be prevented. The OVP protection circuit triggers once VLED crosses a predefined level. As a result the DLPA3005 will be switched off.

Question) If LEDs aren't connected at power on, it looks like the power for DMD is not supplied too. Is this effect of  "7.3.2.5.2 Ratio Metric Overvoltage Protection"?

 

3) 7.3.4.4.1 Power Good

The DMD HV regulator, DMD buck converters, DMD LDOs, and the LDO_DMD that supports the HV regulator, all have a power good indication. The DMD HV regulator is continuously monitored to check if the output rails DMD_RESET, DMD_VOFFSET and DMD_VBIAS are in regulation. If either one of the output rails drops out of regulation (e.g due to a shorted output or overloading) the DMD_ PG_FAULT bit in register 0x29 is set. Threshold for DMD_RESET is 90% and the thresholds for DMD_OFFSET/ DMD_VBIAS are 86% (rising edge) and 66% (falling edge).


Question) Would you please explain the meanings of "rising edge"  "falling edge" of this part? Does the "rising edge" imply power on situation? Does the "falling edge" imply power off situation?

 

 

Best regards,

Rossinag

 

  • 0
    TI__Genius 10495 points

    Hello Rossinag,

    7.3.2.5.1 Power Good

    Both the Illumination driver and the Illumination LDO have a power good indication. The power good for the driver indicates if the output voltage (VLED) is within a defined window indicating that the LED current has reached the set point. If for some reason the LED current cannot be controlled to the intended value, this fault occurs. Subsequently, bit ILLUM_BC1_PG_FAULT in register 0x27 is set high. The illumination LDO output voltage is also monitored. When the power good of the LDO is asserted it implies that the LDO voltage is below a pre-defined minimum of 80% (rising) or 60% (falling) edge. The power good indication for the LDO is in register 0x27 (V5V5_LDO_ILLUM_PG_FAULT).

    Question) We would like to know the "defind window" of VLED. Is this the VLED_ANODE? If so would you please explain meaning  of  the "0.85x" of min value?

    <TI> Yes, it is VLED_Anode. The defined windows is between 0v and 6.3V for VLED_Anode. The datasheet specifies lowest max VLED with 0.85x of VILLUM_A_B_VIN and a max. value of 6.3V. VILLUM_A_B_IN can be between 6 and 20 V with a typical value of 12V. In case of 6V, 0.85x of 6V would be 5.1V. This would mean that the max. VLED Anode voltage would be in this case 5.1V. 

     

    7.3.4.4.1 Power Good

    The DMD HV regulator, DMD buck converters, DMD LDOs, and the LDO_DMD that supports the HV regulator, all have a power good indication. The DMD HV regulator is continuously monitored to check if the output rails DMD_RESET, DMD_VOFFSET and DMD_VBIAS are in regulation. If either one of the output rails drops out of regulation (e.g due to a shorted output or overloading) the DMD_ PG_FAULT bit in register 0x29 is set. Threshold for DMD_RESET is 90% and the thresholds for DMD_OFFSET/ DMD_VBIAS are 86% (rising edge) and 66% (falling edge).

     

    Question) Would you please explain the meanings of "rising edge"  "falling edge" of this part? Does the "rising edge" imply power on situation? Does the "falling edge" imply power off situation?

    <TI>This means  DMD_OFFSET/DMD_VBIAS voltage is not able to rise above 86% of the intended voltage values in case of a fault condition/power up. The 66% means if it falls below 66% of the intended voltage in case of a fault condition.

    7.3.2.5.2 Ratio Metric Overvoltage Protection

    The DLPA3005 illumination driver LED outputs are protected against open circuit use. In case no LED is connected and the PAD device is instructed to set the LED current to a specific level, the LED voltage (ILLUM_A_FB) will quickly rise and potentially rail to VIN. This should be prevented. The OVP protection circuit triggers once VLED crosses a predefined level. As a result the DLPA3005 will be switched off.

    Question) If LEDs aren't connected at power on, it looks like the power for DMD is not supplied too. Is this effect of  "7.3.2.5.2 Ratio Metric Overvoltage Protection"?

    <TI>What version of DLPA3005 are you using ?


    Best regards,

    Nadine

     

     

  • 0 in reply to Nadine Estermann
    Expert 1705 points

    Hello Nadine,

    Thank you very much for your prompt reply.

    We are using D version of DLPA3005.

    Best regards,

    Rossinag 

  • 0 in reply to Rossinag
    TI__Genius 10495 points
    Hello Rossinag,

    In case no LED are connected the DLPA3005 is powering off completely caused by the over-voltage protection. This includes the DMD voltages.

    Best regards,

    Nadine
  • 0 in reply to Nadine Estermann
    Expert 1705 points

    Hello Nadine,

    Thank you very much for your support.

    Please let me ask some more things in below.

    7.3.2.5.1 Power Good 

    <TI> Yes, it is VLED_Anode. The defined windows is between 0v and 6.3V for VLED_Anode. The datasheet specifies lowest max VLED with 0.85x of VILLUM_A_B_VIN and a max. value of 6.3V. VILLUM_A_B_IN can be between 6 and 20 V with a typical value of 12V. In case of 6V, 0.85x of 6V would be 5.1V. This would mean that the max. VLED Anode voltage would be in this case 5.1V.

    <Question>

    In case of VILUM_A_B_VIN = 12V, the POWERGOOD will be indicatred when 0V≦VLED_Anode≦6.3V . And POWERGODD_FAULT will be indicated if the VLED_Anode > 6.3V . Is this correct understanding?

    7.3.4.4.1 Power Good

    <TI>This means  DMD_OFFSET/DMD_VBIAS voltage is not able to rise above 86% of the intended voltage values in case of a fault condition/power up. The 66% means if it falls below 66% of the intended voltage in case of a fault condition.

     

    <Question>

    Please let me ask you the 66% of the falling edge condition.
    Does this mean after the powered up situation? In other words, after DMD_OFFSET/DMD_BIAS are powered up over 86% of the intended voltage and then it falls down to the under 66% of the intended voltage. This is the falling edge of the POWERGOOD_FAULT case. Is this correct understanding?

    Best regards,

    Rossinag

  • 0 in reply to Rossinag
    TI__Genius 10495 points
    Hello Rossinag,

    Thank you for your question.

    Please allow me some time to get back to you.

    Best regards,

    Nadine
  • 0 in reply to Rossinag
    TI__Genius 10495 points

    Hello Rossinag,

    It is a little bit more complicated than that.

    The Power Good for VLED is related to whether the VLED loop was able to control the LED current to the intended current level (current level you would like to achieve) or not.

    In case the control loop is not able to settle to the set point, a Power Good Fault will be the results. The Power Good Fault is not device threatened so the DLPA3005 will not shutdown.

    The VLED value at which the Power Good Fault occurs depends on the load.

    Falling edge case only applies if the system is running already correctly and a fault condition occurs which causes the voltage to fall below 66% of the intended value.

    Please let me know if you have any further questions.

    Best regards,


    Nadine

  • 0 in reply to Nadine Estermann
    Expert 1705 points

    Hello Nadine,

    Thank you very much for your support.

    Would you please find another question?

    7.3.2.5.1 Power Good 

    <TI> Yes, it is VLED_Anode. The defined windows is between 0v and 6.3V for VLED_Anode. The datasheet specifies lowest max VLED with 0.85x of VILLUM_A_B_VIN and a max. value of 6.3V. VILLUM_A_B_IN can be between 6 and 20 V with a typical value of 12V. In case of 6V, 0.85x of 6V would be 5.1V. This would mean that the max. VLED Anode voltage would be in this case 5.1V.

    <Question (confirmation) >

    In case of VILUM_A_B_VIN = 12V, the POWERGOOD will be indicatred when 0V≦VLED_Anode≦6.3V . And POWERGODD_FAULT will be indicated if the VLED_Anode > 6.3V . Is this correct understanding?

    Thank you and best regards,

    Rossinag

     

  • 0 in reply to Rossinag
    TI__Genius 10495 points

    Hello Rossinag,

    As I mentioned already the VLED value at which the Power Good Fault occurs is depended on the load. This means a power good fault doesn't have to occur for a VLED anode voltage larger than 6.3V. As long as the VLED loop is able to control the LED current to the intended current level no power good fault will be triggered.

    The key factor for the power good fault is not really VLED it is the ability of the VLED loop to settle to the correct current value.

    Best regards,

    Nadine