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Discovery 4000 and software problems

Ridha Horchani
Prodigy 50 points

Dear all

we have 2 problems the first that we can't detect the DMD when we connect the DLP discovery 4100 to the computer using the software "D4100 explorer" , in fact we detect only the card  but not the DMD ( "DMD: no DMD"). have you an idea about this fact?

the second is that we are trying to use labview in order to load an image but  we have not a big idea about labview and how it works can you please send us the code ( programme) used with labview to load an image?

thank you very much

  • 0
    Prodigy 105 points

    Dear Ridha,

    I was having the same problem,  please check the way you connect the board to the DMD they should look folded like it showed in the picture. if you have it connected in the wrong way (flat)  it does not work, the communication is not completed. Try this may be works!

  • 0
    TI__Guru 54245 points

    Hello Ridha.

    Welcome to the DLP/MEMS section of the TI E2E forums.  I am glad you have found your way here.

    I notice the title says, "Discovery 4000 & software problems" but in the post you mention, "we connect the DLP discovery 4100". 

    Could you clarify which kit since the software, although very similar, is not interchangeable?  Also, which DMD do you have?

    Thank you,

    Fizix

  • 0 in reply to Fizix
    Prodigy 40 points

    Hi,

    I wish to use phased reset in my DLP® Discovery™ 4000 development board (.55 XGA) . But i have no idea how to go about it. Currently I am using global reset. Can you suggest what modifications I should incorporate in the fpga code (appsfpga) or if some one could post a sample code which uses phased reset it will be very helpful.


    Varun

  • 0 in reply to Varun AV
    TI__Intellectual 2265 points

    Hi Varun,

    There are 4 different types of resets on the Discovery 4000: global, single, dual and quad. In the AppsFPGA sample code on the KnowledgeBase, it gives an example of each one of these resets. Please keep in mind that each block takes at least 4.5us (5.5us recommended) to reset. and 8us after for the mirrors to settle. Therefore, if you are doing a reset to block A, you may load data to block B, but no operations should be done to block A until at least 12.5us after the reset command is given to block A.

    There is a document on the KnowledgeBase called D4000 AppsFPGA Sample Code Guide (TIDN 2510344) that explains the phased resets in the appsFPGA sample code. It also contains a section of code that does single phased resets.