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DLP 7000, DLP CINEMA - Slow speed data transfer, multiplexing, clocking

Steve Hope
Prodigy 85 points
Other Parts Discussed in Thread: DLPC410, DLP7000

We are currently evaluating the DLP 7000 and DLP Cinema DMD's for an NIR spectrograph application. Our application requires monochromatic DMD formatting - no gray scaling - and updates perhaps once every 15 minutes. Moreover the time required to perform an update can be as slow as a second - speed is not an issue. We would also like to reduce the number of wires from the formatter to the DMD, while also extending the distance between them. With that in mind, we would like to build a custom formatter board with a data transfer rate of perhaps one-hundreth of the current DMD controller.

The DMD 7000 includes many specifications which I question... For example LVDS timing... clock speed is spec'ed at 200Mhz to 400Mhz - Is there a reason 200Mhz is the minimum? Is this the minimum required to do full screen greyscale images at 30FPS? Is there a reason it can't be slower for monochromatic images at one frame per several minutes? The DMD 101 app note shows the memory cells drawn as static ram - that being the case one might assume that you could clock at 1Hz if you wanted to. There is also a spec for skew between busses. If I am not doing video, why is this important? Is there any reason why I can't deliberately clock the busses out a phase, as doing so would allow you to multiplex a single data bus with multiple channels . I think I read somewhere (may be in the DLP3000 data sheet) that the clocks have to run continuously... Are the clocks used for more than just clocking data into the memory cells? One would assume once a new image has been loaded that you could stop the clocks completely.

Any insight would be much appreciated.

  • 0
    TI__Guru 54705 points

    Hello Steve,

    First, welcome to the DLP Advanced Light Control section of the TI-E2E community.

    The 200 MHz minimum limitation is imposed by the controller which is a Xilinx FGPA (Virtex-5 LX30).  The FPGA design PLL structure is made to operate from 200 MHz to 400 MHz.  Somewhere below 200 MHz, the FPGA will not properly sync to the incoming DCLK.

    It is atypical to operate at very slow data rates.  The DLPC410 controller does not have any provision for a speed lower than 200 MHz or a narrower data bus.

    The DLPC410 also expects a continuous clock, even if you are not actively sending data.

    I hope this this helps.

    Fizix

  • 0 in reply to Fizix
    Prodigy 85 points

    Hi Fizix,

    I am still not clear on the 'limitations' of transferring data to the DMD... Hopefully you can clarify...

    The 200 MHz minimum limitation is imposed by the controller which is a Xilinx FGPA (Virtex-5 LX30).  The FPGA design PLL structure is made to operate from 200 MHz to 400 MHz.  Somewhere below 200 MHz, the FPGA will not properly sync to the incoming DCLK.

    To clarify, the Xilinx FPGA is the DLPC410, is that correct?... Or is there a Xilinx FPGA internal to the DMD?

    It is atypical to operate at very slow data rates.  The DLPC410 controller does not have any provision for a speed lower than 200 MHz or a narrower data bus.

    The DLPC410 also expects a continuous clock, even if you are not actively sending data.

    So, we would prefer not to use the DLPC410 because:

    • We want to minimize noise sources in our operating environment. This includes IR (heat), RFI and EMI radiation...The discovery board is is a huge heat source and no doubt radiates RF with clocks running at 400Mhz plus. Our instrument will be operating at a temperature of around 100k (-173C) integrating single photon events over durations of 15 minutes more, during which time the pixel states will remain static.
    • The number of data lines are excessive. Ideally we would like to reduce the number of data by multiplexing.

    So, back to my original questions...

    • Assuming we do not use the DLPC410, is there any reason why the DMD can't transfer data with a much slower clock (say 1Mhz)? 
    • Assuming we do not use the DLPC410, is there any reason why we can't stop the clock after transferring data?
    • Assuming we do not use the DLPC410, is there any reason we can't phase the clocks 90 degrees out of phase on the DLP7000 or 45 degrees out of phase on the cinema device, hence allowing us to multiplex the data lines between channels A, B, (C and D) busses provided we ensure that we do not violate the LVDS specs (3.4mA into a 100 Ohm load)

    Regards,

    Steve

  • 0 in reply to Steve Hope
    TI__Guru 54705 points

    Hello Steve,

    I understand where you are going with this, but TI-DLP Advanced Light Control does not support operating a DMD without its matching controller.  We are unable to warranty parts used in this way. 

    There is a lot going on in the controller that is not at first apparent.  Information in addition to pixel data is communicated to the DMD from the controller and the controller coordinates the timing of this communication with the timing and settings of the Micromirror Clocking Pulse (sometimes referred to a "Mirror Reset").

    These timings are critical for reliable operation of the micromirrors.

    I hope this helps.

    Fizix