documentation...

The register interface is documented here:

http://focus.ti.com/pdfs/dlpdmd/2510328A_PicoProgramGuide.pdf

This suggests that HVGA input can be sent via the CPU interface - presumably this provides a

measure of direct control over the mirrors and would allow them to be parked left or right - does anyone

have any experience of using this?  Physically it looks to be the same interface as the DVI-D with a few more

pins, does anyone know if this can be driven directly via DVI-D or will this have to be a CPU or FPGA driven interface?

and does anyone have experience of doing this?

Cheers,

SA

I am a little lost in the documentation for the pico projector, in some docs it looks like the CPU interface is possible without physically

altering the projector in others it looks like there is a DVI-D receiver in the signal chain which must be physically bypassed to access the CPU

interface - can anyone clarify this please?

Is there a way to use CPU input on the pico projector?

Also the source input select (register 0x04 and register 0x05) appear to have a limited impact on the pico projector.

I am not sure if I have understood this correctly but it looks like the DVI-D receiver cannot be used with the source set to 0x3

and the register 0x05 is ignored.

Can these modes be enabled?

I want to get a 1:1 relationship between input data and pixels and bypass or turn off all the video processing.  register 0x05=0x07 would

be perfect but it seems not to work.

Any advice?

Cheers,

SA

Hi,

The CPU mode shares an interface with the Parallel (RGB) mode on the DPP1505. The documentation reference to the CPU interface is mainly for the chipset level of the Pico system. The Pico kit implementation uses the parallel (RGB) mode of the DPP1505 (This is what goes out to the DVI receiver). The CPU interface signals are not readily accessible on the Pico kit.

The Input Resolution setting (register 0x05, found in the DLP® Pico Chipset Programmer’s Guide) is supported at the Pico system chipset level. For the Pico projector kit the input resolution is based on the input source. For parallel (RGB) the input resolution is VGA, for Internal Test Patterns it is HVGA.

Best regards

So the only way to get the cpu interface (and hence a 1:1 mapping of data to pixels) would be to alter the board?

I notice there was another input 9behind a rubber bung) that does not seem to be documented - can this be used?

Does anyone know how much the a complete chipset costs in small (ie development) quantities?

The VGA->HVGA mangling is very annoying and it looks like there is no simple way to fix this via the pico projector.

Cheers,

SA

Hi

Yes that is correct.

The DPP1505 signals do not come out to the input rubber bung, so this input cannot be used for this.

thanks tsolo, would I be right in thinking the connector behind this rubber bung is J112 on the schematic and just a JTAG for programming

the FPGA and PROM?

Can the PROM  / FPGA be re programmed? and is the original image available for reinstating the orignal functionality.

I simply want to bypass the vdieo processing and get a 1:1 relationship between the data in and the mirrors - if there is a better way

of doing this please suggest!

Cheers,

SA

Assuming the side slot is FPGA JTAG (not looked at the schematics this hard), you should be able to download a new image to the FPGA without affecting the default image in the config memory - it would just reload the normal image when power is cycled.

It probably also wouldn't be too hard to read out the config chip to get  a backup.

Good point - I think the two hardest things about this are going to be (a) finding the right cable to connect to the board and (b) getting the right documentation so as to program the DLP properly according to this thread (b) isn't going to be easy: https://community.ti.com/forums/t/7096.aspx

Cheers,

SA