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DLPC910: LVDS Output Bus Skew

first_name Sceglova
Prodigy 210 points
Part Number: DLPC910


1. On page 53 of the DLPC910 Datasheet (Section 10.1.3.2.1 LVDS Output Bus Skew) the recommended skew from one bus to another is 100-200ps. Have I understood correctly that this is the skew between the corresponding bus clocks? In other words, if, say, we use bus A clock as the reference, bus B clock should be skewed by 100-200 ps relative to bus A clock, bus C clock should be skewed by 100-200 ps relative to bus C clock (equivalent to 200-400ps relative to bus A), and finally bus D clock should be skewed by 100-200ps relative to bus C clock (300-600 ps relative to bus A)?

2. It is also stated that total skew should be kept below the maximum skew for the DMD. On page 17 of the DPL9000 Datasheet it is stated that the skew of channel B relative to channel A should be no more than 1040 ps, and the same for channel D relative to channel C. Does this mean that the skew between channels B and D, B and C, A and D, A and C is irrelevant?

3. On page 54 of the DLPC910 Datasheet in table 29, what exactly is meant by the "bus group trace length"?

4. Could you please clarify how Example 1 and Example 2 in the table relate to the skew requirements? In example 2, why is there no delay between bus A and bus B, and bus C and D even though a 100-200 ps is recommended?

  • 0
    TI__Guru 54705 points

    Hello User,

    1.  Table 29 on page 54 shows a couple if possible examples.  Example 2 is where A & B have no relative skew, C& D have no relative skew, but [A,B] have skew relative to [C,D].  Example 1 is where they all have some relative skew.

    Your proposed solution would work.

    2.  From the DMD's point of view the skew difference from [A,B] to [C,D] is not critical.  It would still be good to keep it below one clock cycle (~2 ns).

    3.  This should be read as (bus group) trace length, not bus (group trace length).  Bus A, B , C, & D are "bus groups" which consist of clock, data & SCTRL lines (see table 29 on page 54).  So this would refer to the mean of the bus under consideration.  Table 28 specifies a max pair-to-pair mismatch of 50 mils (~ 10 ps). So all signals on a given bus should be the mean ± 25 mils.

    4.  The salient point of the examples and guidance on page 53 it that you do not want all four busses synchronized with each other.  Two busses is OK and since [A,B] to [C,D] is not critical then example 2 takes advantage of that fact. 

    The scenario you suggest is ideal, but board layout constrains may drive the actual skew / trance length differences.

    I hope this helps.

    Fizix