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DLPC3430: how to configure DSI port of dlpc3430

Part Number: DLPC3430

AP  connect dlpc3430 by mipi,but i don't know  what  commands should be sent to dlpc3430 by i2c, 

so my question is how to configure DSI port of dlpc3430. i can't find any useful clue about this  from "DLPC343X programmer's guide"

but i find below description  in  "dlps038.pdf".

if a different DSI clock rate is ever needed to support antoher frame rate, I2C command  "write DSI Parameters(BDh)"  must be sent to tell the DLPC3430 the new DSI clock frequency

  • Hello  User,

    Thank you for your interest in our DLP Technology. You are correct you have to send the Write DSI Parameter command to be able to set up the DSI HS clock rate.


    Furthermore you would have to set the input source to external and the video source format to DSI.

    Please also ensure that your firmware which is provided by your optical engine manufacture has DSI enabled.

    Thanks,

    Nadine

  • Hi, thanks for your reply,

    I got the  DSI operations manuals,and I follow below ordering of operations:

    step 1 write image freeze param = 0x01

    step 2 write DSI enable Param = 0x00

    step 3 write source format select param = 0x00

    step 4 write dsi parameters param  = 0x0180

    step 5 write input source select  param = 0x00

    step 6 write image freeze param.

    And i configure AP side  mipi as below

    384MHz clock, 2lane  RGB888/24bit

    now i can't get the right  project images, and it just keep default (checkboard pattern)

    Do you have any idea about current situation?

  • Hello User,


    Have you ensured that DSI is enabled in your firmware provided by the optical engine manufacture ?


    Please see below an example of how to setup DSI:

    ## Write: ImageCrop: 854x480
    W 36 10 00 00 00 00 56 03 e0 01
    ## Write: DisplaySize: 854x480
    W 36 12 00 00 00 00 56 03 e0 01
    ## Write: InputImageSize: 854x480
    W 36 2e 56 03 e0 01
    ## Write: VideoSourceFormatSelect: 0x00=DSI
    W 36 07 00
    ## Write: InputSourceSelect; 0 = External Video Port
    W 36 05 00
    ## Write: DSIHSCLK; 156MHZ=0x9C 152MHZ=0x98 106MHZ=6A 158MHz=0x9E
    W 36 BD 9E 00


    Also please note that our limit for the DSI HS clock is 235 MHZ. Can you please clarify if 384 MHZ is the Data Rate per Lane or the Bit Clock ?

    Thanks,

    Nadine

  • Hi
    I setup DSI like the example you supported,and DSIHSCLCK 156MHZ, 2lane,
    i set ap side as 156Mhz,2lane, 854*480
    but it still project deafult test pattern.
    there is any other commands should be setup?
    thanks
  • ps: and i get the related registers status as below
    [ 341.844558] [1: sh: 2255] beam debug read DSI_PORT_ENABLE(0xD8) 0x 0
    [ 341.845682] [1: sh: 2255] beam debug read READ_EXTERNAL_VIDEO_SOURCE_FORMAT_SELECT(0x08) 0x21
    [ 341.846632] [1: sh: 2255] beam debug read READ_INPUT_SOURCE_SELECT(0x06) 0x 0
    [ 341.848766] [1: sh: 2255] beam debug read READ_DSI_PARAMETERS(0xBE) 0x9c 0
  • Hello User,

    When you referring to the default test pattern do you mean the checkerboard ? If you are still seeing a good checkerboard I assume the controller is not setup correctly for DSI.

    Please also take a look at our requirements regarding the DSI transceiver specified in the DLPC3430 datasheet.

    Best regards,

    Nadine
  • Hi

    Answer your question regarding default pattern, now deafult pattern  is color bars pattern,( I asked optical engine manufacture to provide DSI enabled firmware,so deafult pattern became color bars pattern.)

    Do you have way to help me to check  this issue that was caused by  DSI setup of  AP side or firmware?

    thanks

  • Hello User,

    Can you please send me a picture of the screen after you have send all the I2C commands for DSI ?

    Thanks,

    Nadine
  • Hi
    i sent a picture to you,please check it. it keeps this status after i send all i2c commands. And I'm not sure it was caused by AP side or firmware.
    what do you think regrading current situation?

    thanks
  • Hi please ignore this problems for the moment.
    because I found AP side have not satisfy below rules
    a. Disable BTA (Bus Turn Around) in DSI F/E
    b. Setup TH-prepare and zero parameters in DSI F/E.
    Typical frequency range we support:
    i. 40Mhz-64Mhz = 625ns (Ths_prepare + Ths_zero).
    ii. 65Mhz-94Mhz = 565ns (Ths_prepare + Ths_zero).
    iii. 95Mhz-299Mhz = 465ns (Ths_prepare + Ths_zero).
    c. Enable EOT (End of Packet)
    thanks
  • Hello User,

    I think you already receive additional help from our FAE's. I would like to propose to take it offline from here.

    Thank you,

    Nadine