I inital DLPC4100 ,I do not kone why inital failed. Signal INIT_ACTIVE == 1 all the time.
In inital
1、I assign fllow signal:
dmd_clk_to_ddc_o = clk_50m ;
dmd_ns_flip_o = 1'b0 ;
dmd_comp_data_o = 1'b0 ;
dmd_rst2blkz_o = 1'b0 ;
dmd_wdt_enablez_o = 1'b1 ;
dmd_pwr_floatz_o = 1'b0 ;
2、data bus ,include data、valid、clk, use LVDS interface , To produce through OBUFDS(Xillinx ip).
3、 The data clock is 200M
4、In order to satisfy the clock skew in the Handbook(page 21 Figure 3), I get the phase difference between the data clock signal relative to the effective and generated data of data generated when PLL is generated.
5、Self checking is required when initializing, and the biggest job of self-examination is in Interface training pattern. I can't see how the Interface training pattern should match the other signals from the manual.
I hope accoding this e-mail,Get the following reply：
1、What is the initialization process
2、What should pay attention to in Interface training pattern during the initialization process
3、Tell me why I failed to initialize
4、If there are relevant documents, I hope you can tell me
Thank you!
