DLP4710: connecting 80 pin 104060-8017 Molex

Mario,

You are actually supposed to design for one of either Option or Option 2. Can you elaborate which option you are looking at? We can check your schematic against it.

Best Regards,
Philippe Dollo

Thanks for your support Philippe.

To be clear:

*We are designing a lithography application using the DMD4710 chip.

*We will use the DLPDLCR4710EVM-G2 control board. But we will not use the Young Optics optical engine.

* Basically, for our convenience, we are just replacing the Young Optics DMD4710 PCB with our own design. So we can say that we want to use the same option as Young Optics has.

So the following schematic is to connect de DLP4710 chip to the evaluation board  (DLPDLCR4710EVM-G2) both master DLPC3439 and slave DLPC3439.

 

**********************************************************************

Note1: Because I am using a type A ribbon cable (just like young optics does) the pin 1 (on the molex connector) on the control board goes to pin 80 of the dmd pcb.

Note2:  We are not using the W25Q16JV flash memory. So we are not connecting

FLASH_PWR
EXT_M_SPI_CLK
EXT_M_SPI_DOUT
EXT_M_SPI_DIN
EXT_M_SPI_CSZ
EXT_S_SPI_CLK
EXT_S_SPI_DOUT
EXT_S_SPI_DIN
EXT_S_SPI_CSZ

**********************************************************************

So finally, here comes my question....

**********************************************************************

So under this configuration, and as you can see in the schematic, I have made the following connections:

To MASTER DLPC3439  EVALUATION control board (molex connector):
------------------
M_HS_WDATA_E_P --> D_AP(0)
M_HS_WDATA_E_N --> D_AN(0)
M_HS_WDATA_F_P --> D_AP(1)
M_HS_WDATA_F_N --> D_AN(1)
M_HS_WDATA_G_P --> D_AP(2)
M_HS_WDATA_G_N --> D_AN(2)
[...]
M_HS_WDATA_C_P --> D_AP(6)
M_HS_WDATA_C_N --> D_AN(6)
M_HS_WDATA_D_P --> D_AP(7)
M_HS_WDATA_D_N --> D_AN(7)

To SLAVE DLPC3439 (molex connector):

------------------
S_HS_WDATA_D_P --> D_BP(0)
S_HS_WDATA_D_N --> D_BN(0)
S_HS_WDATA_C_P --> D_BP(1)
S_HS_WDATA_C_N --> D_BN(1)
[...]
S_HS_WDATA_E_P --> D_BP(7)
S_HS_WDATA_E_N --> D_BN(7)

QUESTION

Is the this a correct layout?

Thanks for your time Philippe, and sorry to bother with all this information.

Mario

Hi Mario,

We can have only one same option for both master and slave not both. As philippe asked to share the option which you want but i can not see the reply for that question.

If you have connected master and slave for different options then you need to rework and make the same option for both.

Can you please confirm which option you want, i will review the schematic for that option.

Thanks,
Navneet