DLPD4X00KIT: Time delay in APPS FPGA sample code

Hi ykc,

Thanks for your information.

I checked cnt_e.vhd. I'm not sure which one is related to delay

--active, blank, and pattern counters and enable signals
      cnts_active_cnt_q       : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
      cnts_active_cnten_q     : OUT STD_LOGIC;
      cnts_pattern_cnt_q      : OUT STD_LOGIC_VECTOR (26 DOWNTO 0)

They are also inputs to pgen_e.vhd.

May I ask how to generate delays after loading all rows?

Like delay for 100 ms.

Thanks,

Qiang