CCS/DLPC410: RST_ACTIVE is not asserted regularly

Hi,

Yes, we kept DVALID high during the whole operation (>16T).

We could not fetch output ports with ILA, but we can provide our simulation. The interval between the 2 markers is 16T.

Thanks,

Justin

Hi,

It's a steady logic low

Thanks,

Justin

Hi,

DMD_TYPE:0001, VERSION: 5

When the PLL and LVSD modules are ready, the DCLK will always be provided. And after the initialization, our DVALID is constantly logic high (we checked the LVDS output using oscilloscope).

This is our DCLK measurement, is this a valid one?

In addition, we want to know what is the mechanism of ECP2_M_TP5 (DVALID_A) assertion. Does it indicate directly our DVALID LVDS signal from APP_FPGA, or is it an indication of the validity of the DVALID + DATA  signals? If it is the latter one, and if we measured those signals using an oscilloscope, how can we know if they are valid or not?

Thanks,

Justin

Hi Justin,

Dvalid latches the block and mode settings and indicates start of row operation when it is asserted. It should be deasserted after 16 clocks
Please check Figure 8. DLP7000 / DLP7000UV 2XLVDS DMD Input Data Bus.

When you say Dvalid is constantly high. You mean right after initialization it stays high?
Please try keeping it low, adding some delay after init then assert it.

Please also check Figure 3 of datasheet regarding timing requirements of these signals.

-ykc

Hi,

" It should be deasserted after 16 clocks"

How long should it be deasserted? We now deasserted it for 2 clocks after asserting it for 16 clocks but the TP5 is still not asserted.

"Please try keeping it low, adding some delay after init then assert it."

We now keep it low after init and then assert it.

"Please also check Figure 3 of datasheet regarding timing requirements of these signals."

Both of our NS_FLIP and COMP_DATA are constantly logic low.

"DCLK scopeshot you attached is it differential signal ?"

We found that the LVDS clock gets well after we inserted a GBUF for the reset pin of the LVDS module. This is our DCLK signal now.

Thanks,

Justin

Hi,

We found that when we deasserted the ARSTZ, the INIT_ACTIVE will only be asserted for 14ms, unlike the 220ms assertion on the datasheet.

What could possibly cause this, and will this cause any other problem such as the lack of training pattern lasting time?

Thanks,

Justin

And please we would like to know the mechanism of the ECP2_M_TP5 assertion.

Thanks a lot,
Justin

Hi jkc,

We've been working on how to make DVALID TP assert. And we've confirmed two things as below

1. Our code works properly on the DDC4100, which means that our code meets the operation sequence of DLPC410.

After that, we ported this code to the custom board. The only difference between these two projects is the pin assignment file. Still, it doesn't work on the custom board.

2. Our board contractor did give us a basic working binary code for the board, and this code can demonstrate on the DMD mirror properly. However, we need to port our own code to this platform.

Since we confirmed that our code isn't the problem of the operation sequence (from initialization to continuous row operation).

Can you help us to find where the essential problem is? we can provide more information if u need.

BRs,

Justin