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DLP2000: VSYNC and PCKL settings

Part Number: DLP2000
Other Parts Discussed in Thread: DLPC2607,

What sets the VSYNC and PCLK rates for the DLP LightCrafter Display 2000 EVM? Does the Beaglebone black define the VSYNC and PCLK rates or does the DLPC2607 chip on the evm board command particular values?

Right now I've measured VSYNC=23.6 Hz and PCLK=5.9 MHz using an oscilloscope and pin 27 and pin 28, respectively, on the P1 GPIO header. According to the DLPC2607 it can handle PCLK values as high as 33 mHz.

Thank you for your time.

Jay

  • Jay,

    Welcome to the E2E forums, and thanks for your interest in our DLP technology.

    PCLK is provided by the source (in this case the BeagleBone Black). Meanwhile, the operation of VSYNC on the system is defined by the Sequence Sync mode you've set on the system. You can either have the EVM lock to the VSYNC provided by the source, or operate in free-run mode. See the DLPC2607 programmer's guide for more information:

    https://www.ti.com/lit/ug/dlpu013a/dlpu013a.pdf

    I hope this helps. Let me know if you have further questions.

    Regards,

    Philippe Dollo

  • Thank you Philippe.

    Can you please confirm the following:

    If I program the EVM sequence sync mode parameter (0X1E) to "lock-to-VSYNC" then does the image on the DMD refresh at VSYNC?

    If I program the EVM sequence sync mode parameter (0X1E) to "free-run" then does the image on the DMD refresh at the free-run sequence rate defined by parameter 0x19 (Range is 30 to 72 Hz (default = x0859, 60 Hz))? 

    The above questions are referencing page 27 of the DLPC2607 Software Programmer's Guide.

    Best,

    Jay

  • Jay,

    That's correct.

    - Philippe

  • Hi Philippe,

    I have a few more things I am trying to work out:

    on page 53 of the programmer guide it states:

    "5. Unfreeze the display buffer by setting the freeze or buffer swap disable bit to 0 (I2C address 0xA3).
    (a) The unfreeze operation is synchronized to the vertical sync to avoid tearing."

    I am currently operating the EVM in free run mode (the sequence rate is the default 60 Hz). I am loading a series of still images into the BeagleBone Black's frame buffer and transferring the images across the parallel bus. I am doing this using a for loop. For each still image i am using an unfreeze and freeze command.

    Will the unfreeze command by synchronized to the measured 24 Hz VSYNC of my BeagleBone or the 60 Hz sequence rate of the EVM?

    Thanks,
    Jay

  • Jay,

    Are the images being transferred continuously by the BBB or a single time?

    Regards,

    Philippe Dollo

  • Hi Philippe

    I have 40 different images that I display on the DMD in a sequence. Each mask is loaded on to the DMD across the parallel bus sequentially when I send a trigger to a GPIO pin on the BBB. As a result, I flip through 40 different images on the DMD in a time series. Once the 40 images are sequentially displayed on the DMD I am done. I don't know if you would consider this continuous? I've been treating as a series of still images as I read through the documentation.

    Is there anyway to get on the phone to discuss exactly how I am using the DLP2000 in my particular application. It maybe easier for me to describe.

    Jay

  • Jay,

    Apologies for the late response.

    From your description above it does not sound like you are operating in a continuous mode (images are being loaded individually to the frame buffer, and VSYNC is only being clocked once for each image).

    You may want to use the EVM free-run mode in this case, so that you can supply each image frame at your own pace and let the EVM's internal sequence run continuously. The EVM possesses a frame buffer and will thus be receiving each frame asynchronously.

    Let me know if you want to discuss further offline. Thanks and regards.

    - Philippe Dollo