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VGA - 1024x768-60Hz timing lock issue

Liao JengAn
Prodigy 120 points

Hello,

Actually, we have a problem on the timing lock issue. In our system, the front-end IC converter the VGA analog signal and output to TI’s scaler(ex: DDPxxx). When input a standard XGA(1024x768-60Hz) timing, we found the DDP will wrong detect it as a interlaced signal shown in the TI’s DLP composer tool. Of course, the system can’t lock the signal correctly.

Is there anyone can help to explain the meaning of H-sync pulse count in V-Sync width? Will TI’s autolock algorithm use this information to calculate and determine the input timing resolution? What’s the possible root cause of this problem? Thanks.

  • 0
    TI__Mastermind 30875 points

    Hello Liao JengAn,

    Can you please specify the exact part number of the DLP controller? You may want to contact your local TI support if the part is not listed on the ti.com website. 

    yes the autolock software uses incoming signals pixel clock, hsync, vsync, data[23:0] lines to detect the resolution of the source. You mentioned about the XGA resolution 1024x768 since it is the standard source then it should be detected. you can check the DLP controller datasheet if it is meeting the minimum timing requirement. 

    I suggest you can work with local TI contacts collect the autlock debug log for further support.

    I hope this helps.

    Regards,
    Sanjeev