Need legacy version of dsplib

George Karagoulis

Hello,

I'm trying to build a simple application built off dsplib, but unfortunately it seems my CPU revision is too old for the 3.x dsplib. I have a C5510 DSK from spectrum digital from about 5 years ago, which apparently is revision 2.x. I tried rebuilding dsplib with my cpu version, but it failed because I think the 3.x code is taking advantage of features my CPU doesn't have.

My question is, is there anywhere I can find the legacy 2.x sources? Or more generally, am I doing something wrong and the 3.x sources should work for me after I reconfigure something?

Thanks!

over 10 years ago

0 Sivaraj Kuppuraj over 10 years ago

TI__Mastermind 35645 points

Hi,

Team will work on this and will address your query shortly.

Thanks & regards,

Sivaraj K

0 Steve Tsang over 10 years ago

TI__Mastermind 23785 points

You should be able to read the device revision ID register 0x3804 to determine the silicon revision is either 2.1 (0x6511) or 2.2 (0x6512). C5510 is already obselete, the device used on DSK should be C5510A. The CPU revison is documented in: http://processors.wiki.ti.com/images/f/f4/C55x_CPU_revision.pdf

Try using the -silicon_version option as documented in http://www.ti.com/lit/pdf/spru281 to see if it helps.

Regards.

0 George Karagoulis over 10 years ago in reply to Steve Tsang

Prodigy 150 points

So since the CPU revision table shows the C5510A has revision 2.11, does that mean I'm out of luck when it comes to the latest dsplib? Do you make older versions of dsplib available for download?

0 Steve Tsang over 10 years ago in reply to George Karagoulis

TI__Mastermind 23785 points

2.11 is same as 2.1. It is documented in the footnote.

0 George Karagoulis over 10 years ago in reply to Steve Tsang

Prodigy 150 points

Okay then, let me rephrase my question, and hopefully you'll finally answer me rather than send me to documentation I've read a hundred times already:

So since the CPU revision table shows the C5510A has revision 2.1, does that mean I'm out of luck when it comes to the latest dsplib? Do you make older versions of dsplib available for download?

Are you trying to avoid answering my question directly? The latest dsplib is for cpu versions 3.x and later, am I SOL or not, since I have a version 2.x cpu?? Do you make older versions of dsplib available for download?? How many times must I ask before I get a straight response??

0 Mukul Bhatnagar over 10 years ago in reply to George Karagoulis

TI__Guru* 83745 points

I believe Steve is trying to help you here...
Unfortunately this is an older part, and I think it will be a challenge for you and us to support new development with such an old part and old EVM.

I am not aware of older archives and will likely will not be able to make those available to you beyond what is available on the product folders

You can see the 2007 release at the bottom of the DSPLIB get software page

http://software-dl.ti.com/libs/c55_dsplib/latest/index_FDS.html

If that does not help you, with all the build options and CPU revision table recommendations Steve provided, then please post the error messages that you get and we can try to provide some more guidance. Support will be limited

Please feel free to contact your local TI representative team, if the currently proposed suggestions/solutions are not helping so that they can provide closer guidance.

Regards

Mukul

0 George Karagoulis over 10 years ago in reply to Mukul Bhatnagar

Prodigy 150 points

Thanks Mukul, that answers my question. I found the 2.4 sources at your link and that's exactly what I needed. I am able to build the 2.4 dsplib now, whereas I was unable to build the 3.x library, even after adjusting the CPU configuration in Blt55xx.bat (as I mentioned in my original post), due apparently to certain assembly instructions that aren't implemented on my old CPU revision. That was something I tried long before resorting to this forum. I know I have an old device, but I appreciate your support in spite of that.

I'm sure Steve is trying to help in his own way, but it seems he doesn't even read or understand my questions before telling me to RTFM, and that's very frustrating. I had already guessed that my part was no longer supported a long time ago, but I just wanted to know if you had legacy sources somewhere or if I misunderstood something. He jumped to the conclusion that I don't even know the basics and started repeatedly linking me to documents that I've seen hundreds of times before and which don't answer my question.

Anyways, thanks for the help.

0 Mark M over 10 years ago in reply to Mukul Bhatnagar

TI__Mastermind 30110 points

FYI - here are steps for rebuilding the DSPLIB for different CPU Rev: http://processors.wiki.ti.com/index.php/DSPLIB#Q:_How_can_I_rebuild_the_DSPLIB_v2.40.00_library_for_a_newer_CPU_rev._3.x.3F

Since C5510A is CPU Revision 2.11, only use the following flags when rebuilding:
-vcore:2.1
-vcpu:2.1
-v5510:2.2
-v5510A

Hope this helps,
Mark

0 George Karagoulis over 10 years ago in reply to Mark M

Prodigy 150 points

Mark, have you tried that? Were you successful? My dsplib refused to build with those settings, with the following build output:

Fullscreen 5432.build.txt Download

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>rem this file is for building DSPLIB in large memory module 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>call dosrun.bat 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM ======================================================================== 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM =  Texas Instruments 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM =  Run this batch file before attempting to build from a command line. 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM =  This file is automatically generated during installation. 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM ======================================================================== 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM =  If you get an "Out of Environment Space" error message running this batch  

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM =  file on Windows 98 or Windows Me type the following line at the C:\CCStudio_v3.3> prompt  

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM =  to start a new copy of the Windows Command Interpreter with 2K of Environment Space. 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM      COMMAND /E:2048 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>REM ======================================================================== 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>SET PATH=C:\ti\ccsv5\tools\compiler\c5500_4.4.1\bin;C:\ti\ccsv5\tools\compiler\c5500_4.4.1\bin;C:\ProgramData\Oracle\Java\javapath;C:\Perl64\site\bin;C:\Perl64\bin;C:\Program Files (x86)\Python27;C:\Program Files (x86)\Python27\Scripts;C:\Program Files (x86)\Business Objects\Common\3.5\bin\NOTES\;C:\Program Files (x86)\Business Objects\Common\3.5\bin\NOTES\DATA\;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\Program Files\ThinkPad\Bluetooth Software\;C:\Program Files\ThinkPad\Bluetooth Software\syswow64;C:\Program Files\Broadcom\WHL\;C:\Program Files\Broadcom\WHL\syswow64;C:\Program Files\Broadcom\WHL\SysWow64\syswow64;C:\Program Files (x86)\Common Files\Ulead Systems\MPEG;C:\Program Files\Common Files\Lenovo;C:\SWTOOLS\ReadyApps;C:\Program Files (x86)\Intel\Services\IPT\;C:\Program Files (x86)\Common Files\Lenovo;C:\Program Files (x86)\Common Files\lenovo\easyplussdk\bin;C:\Program Files (x86)\Lenovo\Access Connections\;C:\Program Files (x86)\MATLAB\R2013b\bin;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files (x86)\Git\cmd;C:\mingw-builds\x64-4.8.1-posix-seh-rev5\mingw64\bin;C:\Qt\4.8.6_mingw64\bin;C:\Program Files (x86)\Java\jre7\bin;c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;c:\Program Files (x86)\Microsoft SQL Server\100\DTS\Binn\;C:\Program Files\OpenVPN\bin;C:\Program Files (x86)\Inno Setup 5;C:\Program Files\Microsoft Windows Performance Toolkit\;C:\Program Files\doxygen\bin;C:\Program Files (x86)\VisualSVN Server\bin;C:\Program Files (x86)\Symantec\VIP Access Client\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\MATLAB\R2011a\bin;C:\Program Files (x86)\Vector ICD Manager 2.0.21\Exec32;C:\Program Files\TortoiseGit\bin;C:\Program Files (x86)\Pico Technology\PicoScope6\;C:\ti\ccsv6\tools\compiler\c5500_4.4.1\bin;; 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>rem SET TI_DIR=C:\CCStudio_v3.3 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>SET C55X_A_DIR="C:\ti\ccsv5\tools\compiler\c5500_4.4.1\include";"C:\ti\ccsv5\tools\compiler\c5500_4.4.1\lib" 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>SET C55X_C_DIR="C:\ti\ccsv5\tools\compiler\c5500_4.4.1\include";"C:\ti\ccsv5\tools\compiler\c5500_4.4.1\lib" 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>set OPTIONS= -g -ml -vcpu:2.1 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>set DSPLIB=55xdspx_r3 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>set SRC=55x_src 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>set FILES= *.asm 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>set EXT=asm 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>rem built library in SRC dir  and then copy to root 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>del 55xdspx_r3.src 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>del 55xdspx_r3.lib 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03>cd 55x_src 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>del *.obj 
Could Not Find C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src\*.obj

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>cl55  -g -ml -vcpu:2.1  *.asm 
[abias.asm]
"abias.asm", REMARK   at line 202: [R5688] A localrepeat may be corrupted when
                                           C54CM == 1 (see the C55x silicon
                                           exceptions errata; Advisory CPU_85)
	        RPTBLOCAL OuterLoopEnd-1; port of RPTBLOCAL OuterLoopEnd-1

"abias.asm", REMARK   at line 242: [R5503] This instruction will not behave
                                           correctly when it follows the MMR
                                           write of SP/SSP on line 231 and
                                           interrupts are enabled. Ensure at
                                           least 4 cycles occur between these
                                           two instructions. (see the C55x
                                           silicon exceptions errata; Advisory
                                           CPU_84)
	        XCC    TC1

"abias.asm", REMARK   at line 242: [R5503] This instruction will not behave
                                           correctly when it follows the MMR
                                           write of SP/SSP on line 227 and
                                           interrupts are enabled. Ensure at
                                           least 4 cycles occur between these
                                           two instructions. (see the C55x
                                           silicon exceptions errata; Advisory
                                           CPU_84)
	        XCC    TC1

"abias.asm", REMARK   at line 244: [R5503] This instruction will not behave
                                           correctly when it follows the MMR
                                           write of SP/SSP on line 231 and
                                           interrupts are enabled. Ensure at
                                           least 4 cycles occur between these
                                           two instructions. (see the C55x
                                           silicon exceptions errata; Advisory
                                           CPU_84)
	        XCC    TC1

"abias.asm", REMARK   at line 244: [R5503] This instruction will not behave
                                           correctly when it follows the MMR
                                           write of SP/SSP on line 227 and
                                           interrupts are enabled. Ensure at
                                           least 4 cycles occur between these
                                           two instructions. (see the C55x
                                           silicon exceptions errata; Advisory
                                           CPU_84)
	        XCC    TC1

"abias.asm", REMARK   at line 244: [R5505] This instruction will not behave
                                           correctly when it follows the MMR
                                           read of SP/SSP on line 242 and
                                           interrupts are enabled. Ensure at
                                           least 2 cycles occur between these
                                           two instructions. (see the C55x
                                           silicon exceptions errata; Advisory
                                           CPU_84)
	        XCC    TC1

"abias.asm", REMARK   at line 247: [R5503] This instruction will not behave
                                           correctly when it follows the MMR
                                           write of SP/SSP on line 231 and
                                           interrupts are enabled. Ensure at
                                           least 4 cycles occur between these
                                           two instructions. (see the C55x
                                           silicon exceptions errata; Advisory
                                           CPU_84)
	        XCC    TC1

"abias.asm", REMARK   at line 247: [R5505] This instruction will not behave
                                           correctly when it follows the MMR
                                           read of SP/SSP on line 244 and
                                           interrupts are enabled. Ensure at
                                           least 2 cycles occur between these
                                           two instructions. (see the C55x
                                           silicon exceptions errata; Advisory
                                           CPU_84)
	        XCC    TC1

[add.asm]
"add.asm", REMARK   at line 135: [R5688] A localrepeat may be corrupted when
                                         C54CM == 1 (see the C55x silicon
                                         exceptions errata; Advisory CPU_85)
		RPTBLOCAL	LoopEnd-1                  ; port of RPTBLOCAL  LoopEnd-1                  

"add.asm", REMARK   at line 137: [R5673] If accumulator shift left operation
                                         overflows, M40 == 0, SXMD == 0, and
                                         C54CM == 0, then the shift operation
                                         may not yield the appropriate
                                         saturated result; (see the C55x
                                         silicon exceptions errata; Advisory
                                         CPU_89)
		        MOV	HI(AC0 << T0), *AR2+    ; shift right by 0 or 1

[araw.asm]
"araw.asm", REMARK   at line 198: [R5688] A localrepeat may be corrupted when
                                          C54CM == 1 (see the C55x silicon
                                          exceptions errata; Advisory CPU_85)
	        RPTBLOCAL OuterLoopEnd-1; port of RPTBLOCAL OuterLoopEnd-1

"araw.asm", REMARK   at line 232: [R5503] This instruction will not behave
                                          correctly when it follows the MMR
                                          write of SP/SSP on line 217 and
                                          interrupts are enabled. Ensure at
                                          least 4 cycles occur between these
                                          two instructions. (see the C55x
                                          silicon exceptions errata; Advisory
                                          CPU_84)
	        XCC    TC1

"araw.asm", REMARK   at line 232: [R5503] This instruction will not behave
                                          correctly when it follows the MMR
                                          write of SP/SSP on line 213 and
                                          interrupts are enabled. Ensure at
                                          least 4 cycles occur between these
                                          two instructions. (see the C55x
                                          silicon exceptions errata; Advisory
                                          CPU_84)
	        XCC    TC1

"araw.asm", REMARK   at line 234: [R5503] This instruction will not behave
                                          correctly when it follows the MMR
                                          write of SP/SSP on line 217 and
                                          interrupts are enabled. Ensure at
                                          least 4 cycles occur between these
                                          two instructions. (see the C55x
                                          silicon exceptions errata; Advisory
                                          CPU_84)
	        XCC    TC1

"araw.asm", REMARK   at line 234: [R5503] This instruction will not behave
                                          correctly when it follows the MMR
                                          write of SP/SSP on line 213 and
                                          interrupts are enabled. Ensure at
                                          least 4 cycles occur between these
                                          two instructions. (see the C55x
                                          silicon exceptions errata; Advisory
                                          CPU_84)
	        XCC    TC1

"araw.asm", REMARK   at line 234: [R5505] This instruction will not behave
                                          correctly when it follows the MMR
                                          read of SP/SSP on line 232 and
                                          interrupts are enabled. Ensure at
                                          least 2 cycles occur between these
                                          two instructions. (see the C55x
                                          silicon exceptions errata; Advisory
                                          CPU_84)
	        XCC    TC1

"araw.asm", REMARK   at line 236: [R5503] This instruction will not behave
                                          correctly when it follows the MMR
                                          write of SP/SSP on line 217 and
                                          interrupts are enabled. Ensure at
                                          least 4 cycles occur between these
                                          two instructions. (see the C55x
                                          silicon exceptions errata; Advisory
                                          CPU_84)
	        XCC    TC1

"araw.asm", REMARK   at line 236: [R5505] This instruction will not behave
                                          correctly when it follows the MMR
                                          read of SP/SSP on line 234 and
                                          interrupts are enabled. Ensure at
                                          least 2 cycles occur between these
                                          two instructions. (see the C55x
                                          silicon exceptions errata; Advisory
                                          CPU_84)
	        XCC    TC1

"araw.asm", REMARK   at line 236: [R5505] This instruction will not behave
                                          correctly when it follows the MMR
                                          read of SP/SSP on line 232 and
                                          interrupts are enabled. Ensure at
                                          least 2 cycles occur between these
                                          two instructions. (see the C55x
                                          silicon exceptions errata; Advisory
                                          CPU_84)
	        XCC    TC1

[arct2.asm]
"arct2.asm", REMARK   at line 96: [R5688] A localrepeat may be corrupted when
                                          C54CM == 1 (see the C55x silicon
                                          exceptions errata; Advisory CPU_85)
	 ||     RPTBLOCAL OuterLoopEnd-1; port of || RPTBLOCAL OuterLoopEnd-1

"arct2.asm", REMARK   at line 125: [R5688] A localrepeat may be corrupted when
                                           C54CM == 1 (see the C55x silicon
                                           exceptions errata; Advisory CPU_85)
	                RPTBLOCAL InnerLoopEnd-1; port of RPTBLOCAL InnerLoopEnd-1

"arct2.asm", ERROR!   at line 127: [E0800] Illegal Parallel Pair: same operator
                                           (D-Unit) used by both instructions
	                        MPY     T0, AC2, AC3
	                     || SFTS    AC2, #-1, AC0

"arct2.asm", ERROR!   at line 135: [E0800] Illegal Parallel Pair: same operator
                                           (D-Unit) used by both instructions
	                MPY     T0, AC2, AC3
	             || SFTS    AC0, #1

"arct2.asm", ERROR!   at line 145: [E0800] Illegal Parallel Pair: same operator
                                           (D-Unit) used by both instructions
	                SFTS    AC2, #1
	             || MOV     T3, HI(AC0)        ; C5

"arct2.asm", ERROR!   at line 149: [E0800] Illegal Parallel Pair: same operator
                                           (D-Unit) used by both instructions
	                MACR    AC0, T0, AC1, AC0
	             || MOV     AR4, HI(AC1)       ; C3

"arct2.asm", ERROR!   at line 149: [E0800] Illegal Parallel Pair: same bus
                                           resource ((null)) used by both
                                           instructions
	                MACR    AC0, T0, AC1, AC0
	             || MOV     AR4, HI(AC1)       ; C3

"arct2.asm", ERROR!   at line 151: [E0800] Illegal Parallel Pair: same operator
                                           (D-Unit) used by both instructions
	                MACR    AC0, T0, AC1, AC0
	             || MOV     AR5, HI(AC1)       ; C2

"arct2.asm", ERROR!   at line 151: [E0800] Illegal Parallel Pair: same bus
                                           resource ((null)) used by both
                                           instructions
	                MACR    AC0, T0, AC1, AC0
	             || MOV     AR5, HI(AC1)       ; C2

"arct2.asm", ERROR!   at line 153: [E0800] Illegal Parallel Pair: same operator
                                           (D-Unit) used by both instructions
	                MACR    AC0, T0, AC1, AC0
	             || MOV     AR6, HI(AC1)       ; C1

"arct2.asm", ERROR!   at line 153: [E0800] Illegal Parallel Pair: same bus
                                           resource ((null)) used by both
                                           instructions
	                MACR    AC0, T0, AC1, AC0
	             || MOV     AR6, HI(AC1)       ; C1

"arct2.asm", ERROR!   at line 171: [E0200] Total size of all instructions in
                                           LOCALREPEAT body is too large (is
                                           119 bytes, must be <= 60 bytes.)
                                           Using the .localalign directive or a
                                           .align 4 directive to align the loop
                                           may allow several additional bytes
                                           within the loop body.
	                MOV     HI(AC0), *AR2+        

"arct2.asm", REMARK   at line 171: [R5682] This outer loop contains a nested
                                           localrepeat that may cause execution
                                           to terminate if an iteration of the
                                           nested localrepeat is interrupted;
                                           (see the C55x silicon exceptions
                                           errata; Advisory CPU_116)
		}

10 Assembly Errors, No Assembly Warnings

Errors in Source - Assembler Aborted

>> Compilation failure

>> Compilation failure

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>ar55 -r 55xdspx_r3.src *.asm ..\include\*.h 
  ==>  new archive '55xdspx_r3.src'
  ==>  building archive '55xdspx_r3.src'

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>ar55 -r 55xdspx_r3.lib *.obj 
  ==>  new archive '55xdspx_r3.lib'
  ==>  building archive '55xdspx_r3.lib'

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>copy 55xdspx_r3.src .. 
        1 file(s) copied.

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>copy 55xdspx_r3.lib .. 
        1 file(s) copied.

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>del *.src 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>del *.lib 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>dir *.obj  1>>..\junk.txt 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>del *.obj 

C:\c55_lp\c55_dsplib_3.00\c55_dsplib_03.00.00.03\55x_src>cd ..

The problems start with arct2.asm:

"arct2.asm", ERROR!   at line 127: [E0800] Illegal Parallel Pair: same operator
                                           (D-Unit) used by both instructions
                            MPY     T0, AC2, AC3
                         || SFTS    AC2, #-1, AC0

Let me reiterate that I was successful building the 2.4 version of dsplib, so strictly speaking I don't need version 3, but if you can somehow figure out how to get it to build with my CPU revision, I would be very grateful! Ideally I would keep all the same functions (i.e. not just comment out whatever doesn't build). I guess I could just copy over the offending sources with the 2.4 versions, but I can see that getting very messy, non-portable and possibly introducing bugs.

Thanks

Processors

Processors forum

Need legacy version of dsplib