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CSL I2C build problem

Other Parts Discussed in Thread: TMS320C5505, TCA6416

Hi, I'm trying to use CSL v3.01 and there's a build problem.

There's a function:

/** ============================================================================
 *   @n@b I2C_read
 *
 *   @b Description
 *   @n Receives the I2C data from the I2C device.
 *
 *   @b Arguments
 *   @verbatim
            i2cRdBuf           I2C Data buffer pointer
            dataLength         Number bytes to receive
            slaveAddr          Address of the slave device
            masterMode         Master mode flag
            startStopFlag      Flag for the start and stop bits
            timeout            Time out variable
            checkBus           Check Bus busy flag
     @endverbatim
 *
 *   <b> Return Value </b>  CSL_Status
 *   @li       CSL_SOK                      - Returned for success
 *   @li       CSL_ESYS_INVPARAMS           - Invalid parameter
 *   @li       CSL_I2C_BUS_BUSY_ERR         - Busy Bit Error
 *   @li       CSL_I2C_TIMEOUT_ERROR        - Time out Error has occured
 *   @li       CSL_I2C_RECEIVE_OVERFLOW_ERR - Recieve Register over flow error
 *
 *   <b> Pre Condition </b>
 *   @n  I2C_init and I2C_config/I2C_setup should be called successfully
 *
 *   <b> Post Condition </b>
 *   @n  Receives the I2C data
 *
 *   @b Modifies
 *   @n I2C data buffer
 *
 *   @b Example
 *   @verbatim
            #define CSL_I2C_SYS_CLK          (12)    // In MHz
            #define CSL_I2C_BUS_FREQ         (10)    // In KHz
            #define CSL_I2C_DATA_SIZE        (16)
            #define CSL_I2C_EEPROM_ADDR      (0x50)
            #define CSL_I2CEEPROM_ADDR_SIZE  (2)

            Uint16           i2cDataBuf[CSL_I2C_DATA_SIZE];
            CSL_Status       status;
            CSL_I2cSetup     i2cSetup;

            i2cSetup.addrMode    = CSL_I2C_ADDR_7BIT;
            i2cSetup.bitCount    = CSL_I2C_BC_8BITS;
            i2cSetup.loopBack    = CSL_I2C_LOOPBACK_DISABLE;
            i2cSetup.freeMode    = CSL_I2C_FREEMODE_DISABLE;
            i2cSetup.repeatMode  = CSL_I2C_REPEATMODE_DISABLE;
            i2cSetup.ownAddr     = CSL_I2C_OWN_ADDR;
            i2cSetup.sysInputClk = CSL_I2C_SYS_CLK;
            i2cSetup.i2cBusFreq  = CSL_I2C_BUS_FREQ;

            status = I2C_init(CSL_I2C0);
            ....
            status = I2C_setup(&i2cSetup);
            ....
            ....
            status = I2C_read(i2cDataBuf, CSL_I2C_DATA_SIZE, CSL_I2C_EEPROM_ADDR,
                              TRUE, 1, CSL_I2C_MAX_TIMEOUT, FALSE);
     @endverbatim
 *  ============================================================================
 */
CSL_Status I2C_read(Uint16    *i2cRdBuf,
                    Uint16    dataLength,
                    Uint16    slaveAddr,
                    Uint16    *subAddr,
                    Uint16    subAddrLength,
                    Bool      masterMode,
                    Uint16    startStopFlag,
                    Uint16    timeout,
                    Bool      checkBus)
{
	volatile Uint16 looper;
	Uint16          dataCount;
	Uint16          statusByte;
	CSL_Status      status;
	Bool            writeSubAddr;

	writeSubAddr = (subAddrLength > 0)?TRUE:FALSE;

	if((i2cRdBuf != NULL) && (dataLength !=0))
	{
		if ((subAddr != NULL) && (writeSubAddr == TRUE)) /* Write the Sub Address */
		{
			/* check for bus busy */
			for(looper = 0; looper < timeout; looper++)
			{
				statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR, I2C_ICSTR_BB);
				if(statusByte == FALSE)
				{
					break;
				}
			}

			if(looper >= timeout)
			{
				/* bus busy timeout error */
				return(CSL_I2C_BUS_BUSY_ERR);
			}

			if(masterMode == TRUE)
			{
				/* Set the slave address */
				CSL_FINS(i2cHandle->i2cRegs->ICSAR, I2C_ICSAR_SADDR, slaveAddr);

				/* Enable Master mode */
				CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, SET);

				/* Set the start bit */
				if((startStopFlag & CSL_I2C_START) == CSL_I2C_START)
				{
					CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STT, SET);
				}
			}
			else
			{
				/* Disable Master mode */
				CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, CLEAR);
			}

			/* Set the Tx mode */
			CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_TRX, SET);

			/* Set the data length */
			CSL_FINS(i2cHandle->i2cRegs->ICCNT, I2C_ICCNT_ICDC, (subAddrLength));

			for(dataCount = 0; dataCount < subAddrLength; dataCount++)
			{
				/* Check for ICXRDY status */
				for(looper = 0; looper < timeout; looper++)
				{
					statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR,
										  I2C_ICSTR_ICXRDY);
					if(statusByte == TRUE)
					{
						break;
					}
				}

				if(looper >= timeout)
				{
					return(CSL_I2C_TIMEOUT_ERROR);
				}

				/* Write data to the data Tx register */
				CSL_FINS(i2cHandle->i2cRegs->ICDXR, I2C_ICDXR_D, *subAddr++);

				for(looper = 0; looper < timeout; looper++)
				{
					/* Check for NACK status */
					statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR,
										  I2C_ICSTR_NACK);
					if(statusByte == FALSE)
					{
						break;
					}
				}

				if(looper >= timeout)
				{
					return(CSL_I2C_NACK_ERR);
				}
			}
			/* Give some delay */
			for(looper = 0; looper < timeout; looper++){;}
		}

		/* Set the Rx mode */
		CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_TRX, CLEAR);

		/* Set the data length */
		CSL_FINS(i2cHandle->i2cRegs->ICCNT, I2C_ICCNT_ICDC, dataLength);

		if(masterMode == TRUE)
		{
			/* Set the slave address */
			CSL_FINS(i2cHandle->i2cRegs->ICSAR, I2C_ICSAR_SADDR, slaveAddr);

			/* Enable Master mode */
			CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, SET);

			/* Set the start bit */
			if((startStopFlag & CSL_I2C_START) == CSL_I2C_START)
			{
				CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STT, SET);
			}
		}
		else
		{
			/* Disable Master mode */
			CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, CLEAR);
		}

		if(checkBus == TRUE)
		{
			/* check for bus busy */
			for(looper = 0; looper < timeout; looper++)
			{
				statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR, I2C_ICSTR_BB);
				if (statusByte == FALSE)
				{
					break;
				}
			}

			if(looper >= timeout)
			{
				/* bus busy timeout error */
				return(CSL_I2C_BUS_BUSY_ERR);
			}
		}

		for(dataCount = 0; dataCount < dataLength; dataCount++)
		{
			/* Check for ICRRDY status */
			for(looper = 0; looper < timeout; looper++)
			{
				statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR,
				                      I2C_ICSTR_ICRRDY);
				if(statusByte == TRUE)
				{
					break;
				}
			}

			if(looper >= timeout)
			{
				return(CSL_I2C_TIMEOUT_ERROR);
			}

			/* Read data from the data Rx register */
			*i2cRdBuf++ = CSL_FEXT(i2cHandle->i2cRegs->ICDRR, I2C_ICDRR_D);

			/* Check for Overflow status */
			statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR, I2C_ICSTR_RSFULL);
			if(statusByte == TRUE)
			{
				return(CSL_I2C_RECEIVE_OVERFLOW_ERR);
			}
		}
	}
	else
	{
		return(CSL_ESYS_INVPARAMS);
	}

	/* Set the stop bit */
	if((startStopFlag & CSL_I2C_STOP) == CSL_I2C_STOP)
	{
		CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STP, SET);
	}

	return(CSL_SOK);
}

As you can see the function is used like this:

status = I2C_read(i2cDataBuf, CSL_I2C_DATA_SIZE, CSL_I2C_EEPROM_ADDR,
                              TRUE, 1, CSL_I2C_MAX_TIMEOUT, FALSE);

and it's 7 parameters, but the body of the function has 9 parameters:

CSL_Status I2C_read(Uint16    *i2cRdBuf,
                    Uint16    dataLength,
                    Uint16    slaveAddr,
                    Uint16    *subAddr,
                    Uint16    subAddrLength,
                    Bool      masterMode,
                    Uint16    startStopFlag,
                    Uint16    timeout,
                    Bool      checkBus)

That's why there are errors when I'm trying to compile it:

#167 too few arguments in function call    csl_i2c_ioExpander.c    /proG-demo/CSL/src    line 223    C/C++ Problem

So what to do this that? Thanks.