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How does DARAM work? (or memory access timing and sequencing)

Brian Willoughby
Genius 4630 points

I would like to ascertain more of details about how DARAM works, particularly how this relates to resource contention.

When I first read that DARAM is Dual Access, I assumed the old definition of Dual Port, meaning two simultaneous accesses.  But after reading volumes of information concerning the C5500, I learned that DARAM actually has the ability to be accessed twice in a single cycle, once early in the cycle and again later in the cycle, but not actually simultaneously.  Please correct me if I misinterpreted this.

I also understand that SARAM is perfect for code, since the DSP will never try to access code memory more than once.  SARAM also seems appropriate for data accessed via CDP.  I further assume that if SARAM can only be accessed once per cycle, then it must be available at the correct time (early/late) needed by the instruction fetch or CDP access.  So which phase is it?

If there are two memory access phases per cycle, then what are their restrictions?  Is one read-only?  Is one DARAM-only?  Does the DMA have access to only one of these memory phases?  If not, does DMA have preference for one of them?  There have been a few hints here that suggest the latter, but my own testing does not confirm this.

I tried searching for this sort of information in the many C5500 documents, but could not find anything.

  • 0
    TI__Mastermind 23785 points

    Brian,

    The DARAM dual access in the C5515, C5514, C5505 & C5504 family is the 2 access in one cycle. It can be 2 reads, 2 writes or one each. This applies to individual blocks. So,  multiple blocks can be accessed by different masters.

    The SARAM is once per cycle One read or one write.

    There is no preference for the DMA. Only that USB has no access to DARAM. This is the design architecture. DMA has less priority than CPU and program loading has even higher priority than data.

    Regards.

  • 0 in reply to Steve Tsang
    Genius 4630 points

    Thanks for the reply, Steve.

    I totally forgot to mention that I am working with the C5506, and the DSK5509A.  Does this family have the same USB restriction to SARAM?  Any other restrictions in the C5509A family?

    I get the impression that using RPTBLOCAL would help reduce the program loading bandwidth, and potentially open up more bandwidth for DMA, although I have all code in SARAM and less than half of my DMA data in SARAM.

  • 0 in reply to Brian Willoughby
    TI__Mastermind 23785 points

    The C5509A can access both DARAM & SARAM via the DMA engine. It supports the Full Speed Slave mode only. If you are not already aware.

  • 0 in reply to Steve Tsang
    Genius 4630 points

    Thanks for the clarification, Steve.

    I have subsequently discovered what might be causing my bottleneck.  While the core of the DSP has 3 read busses and 2 write busses, allowing for multiple simultaneous accesses to both DARAM and SARAM, it seems that the DMA engine has only a single bus for each of DARAM and SARAM.  Thus, if two DMA channels compete for DARAM at the same time, one will experience a Sync Drop Event.

    In addition, it seems that USB DMA accesses which are triggered at the same time as a DARAM or SARAM access are even more prone to Sync Drop.  I am looking into ways to skip the USB DMA entirely, and perhaps access the USB memory directly without DMA, so as to avoid the significant DMA Sync Drop losses that I am experiencing in my firmware.

    Any further information detailing the restrictions here would be helpful.