Clear SRIO LSU transactions using PRVID.

Chaitanaya Chhibbar

Prodigy 80 points

Hi,

I am using SRIO peripheral on TI 6618 DSP.

The shadow register configuration is set to default i.e. each LSU is using 4 shadow registers.

Error Scenario: LSU is locked by one core say core 0 and need to be unlocked using the CBUSY bit.

As per the SRIO user guide for the keystone device( Literature Number: SPRUGW1A, October 2011 )

" To overcome this issue, a CBUSY (clear busy) bit is present in the WO version of LSU_REG. A master on the device can intervene and set the CBUSY bit, along with the PRIVID information. If the PRIVID matched the information that came when the LSU was locked originally, the hardware will release the busy bit."

Can you please let me know from where i can read the PRVID to be used for unlocking the LSU?

I have tried PRVID - 9 with the CSL API (-- CSL_SRIO_CancelLSUTransaction( gSrioHandle, lsuNumber, privID) --). But this is not releasing the LSUs.

Please let me know the procedure of reading PRVID and the releasing the LSUs using PRVID.

Regards,

Chaitanaya

over 14 years ago

0 tscheck over 14 years ago

TI__Mastermind 23525 points

There is no way to read the PrivID of the master that programmed/locked the LSU. Handling of such an error case has to be predetermined/managed in software. For example, it is predetermined that core 4 will detect and clear such error cases, and it is determined that LSU is used only by core 0. This is just an example, but you understand what I'm suggesting here. The PRIVID mapping to individual master is found in the data manual. For example: http://www.ti.com/lit/ds/symlink/tms320c6678.pdf table 7-51.

Regards,

Travis

0 Chaitanaya Chhibbar over 14 years ago in reply to tscheck

Prodigy 80 points

Thanks Travis for the information..

I have tried to release the using the privid 0 for core 0 but that is not working...

- LSU 0 is being used by core 0

Is there any thing else which i need to do with this or does it require some time to release the shadow registers ?

eg. privID = gCoreId;

CSL_SRIO_CancelLSUTransaction( gSrioHandle, lsuNumber, privID);

0 tscheck over 14 years ago in reply to Chaitanaya Chhibbar

TI__Mastermind 23525 points

I'm not sure what your proceedure is for testing this. Is it something like:

1) Core 0 reads the Reg6 of LSU 0 to lock it, but then doesn't write any of the other Registers including #5 to complete the transaction

2) Core 1 reads the Reg6 of LSU 0 and sees BSY set

3) Core 1 then attempts to unlock by writing Reg6 of LSU0, setting the CBUSY bit and PRIVID = 0.

Is that right?

How are you verifying that LSU0 doesn't unlock? If you are reading Reg6 again to determine this, then BSY should be 0, but you are locking it again so any subsequent read is going to be 1. You can also check that the CC=0b111 in the corresponding LSU0_STAT register.

If you are doing at this, I don't see a problem. Have you verified that the CSL is correct by trying to write the Reg6 directly with a value instead of using the CSL_SRIO_CancelLSUTransaction function?

Regards,

Travis

0 Chaitanaya Chhibbar over 14 years ago in reply to tscheck

Prodigy 80 points

Hi Travis,

Thanks for the reply...

I have tried the below procedure but its not working. Kindly help me to figure out the issue.

---> One Lsu is dedicated per core i.e. only if Lsu 0 is being used by core 0 then no other core uses it.

Operation details:

1. Make sure there is space in the Shadow registers to write i.e check for busy bit

2. If shadow register is avaliable then

--> Get the LSU Context and Transaction Information.

--> Configure the LSU for the transaction.

3. If there is no LSU register available then cancel an LSU Transaction previously submitted using cbusy and the privid, and again check for shadow registers availability.

---> If shadow register is avaliable then

- Get the LSU Context and Transaction Information.

- Configure the LSU for the transaction.

---> If shadow register is not available then return error try again while initiating next transaction.

Observation:

LSU shadow registers are not released using cbusy and the privid until the time out.

Code snippet:

--------------------------------------------------------------------------------------------------------------------------------------------

	waitCount = 0xFFFF;
	/* Make sure there is space in the Shadow registers to write */
	while (waitCount)
	{
		if (CSL_SRIO_IsLSUFull (gSrioHandle, lsuNumber) == 0)
			break;

		waitCount--;
	}

	if(waitCount == 0)
	{
		SYS_Printf("LSU shadow registers not available - Cancel LSU Transaction. \n");
		privID = gCoreId;
		CSL_SRIO_CancelLSUTransaction( gSrioHandle, lsuNumber, privID);

                 waitCount = 0xFFFF;
		/* Make sure there is space in the Shadow registers to write */
		while (waitCount)
		{
			if (CSL_SRIO_IsLSUFull (gSrioHandle, lsuNumber) == 0)
				break;

			waitCount--;
		}

		if(waitCount == 0)
		{
			SYS_Printf("LSU shadow registers not available. \n");
			return ERROR;
		}
	}

	/* Get the LSU Context and Transaction Information. */
	CSL_SRIO_GetLSUContextTransaction (gSrioHandle, lsuNumber,&transContextBit, &transId);

	/* Configure the LSU appropriately. */

---------------------------------------------------------------------------------------------------------------------------------------------

CSL appears to be correct by looking at the code.

CSL_IDEF_INLINE void CSL_SRIO_CancelLSUTransaction (    CSL_SrioHandle  hSrio,     Uint8           lsu,    Uint8           privID )
{
    hSrio->LSU_CMD[lsu].RIO_LSU_REG6 = 
            CSL_FMK(SRIO_RIO_LSU_REG6_CBUSY,  1)       |
            CSL_FMK(SRIO_RIO_LSU_REG6_PRIVID, privID);
}

---------------------------------------------------------------------------------------------------------------------------------------------

Please suggest if i need to try any other method.

Regards

Chaitanaya

0 tscheck over 13 years ago in reply to Chaitanaya Chhibbar

TI__Mastermind 23525 points

Chaitanaya,

I think there is a misconception on when and how to unlock the LSU registers. That is why I asked how you were testing this.

Chaitanaya Chhibbar said:
3. If there is no LSU register available then cancel an LSU Transaction previously submitted using cbusy and the privid, and again check for shadow registers availability.

Once a transaction has been written into the LSU shadow registers, it can not be cancelled unless an error condition occurs and the software writes the flush bit to the LSU to delete all submitted transactions in the shadow registers that belong to the SRCID_MAP. The LSU has to be in the error state as described in the user's guide. If you read the reg6 and the FULL bit is set, the LSU is not necessarily in a error condition. And if you read a set FULL bit, the LSU does not become locket to that CPU. The CPU will have to read the register again to check for availability of a shadow register.

A locked LSU is caused by another situation. Essentially, the CPU who aquired the lock (read the reg6, FULL and BSY were 0b0), failed to program the reg5 for some reason. So the LSU is locked to this CPU until reg5 is written, or until the LSU is unlocked with the CBUSY bit and PRIVID info. In normal scenarios, always the LSU BUSY bit is used to arbitrate among different masters requiring access to the LSU. CBUSY is not used except in extreme conditions. The software will need to have a conservative, but robust, policy about determining what an extreme condition is. It will need to account for all masters including the one that is understood to be the overall manager for conditions like this. If the master that is using an LSU does not complete the setup it means that either the software was incorrectly designed or there is a serious problem with that master and I would expect in that case that there is other evidence of the masters condition. Ultimately, if this condition should arise, I would not expect it to be detected and corrected wtihout some real performance impact. The purpose of a feature like CBUSY is more about regaining control of a system rather than saving performance.

So here is the process to follow:

A) Read the Reg6

1) If FULL is set, Goto A

2) If FULL is clear, and BSY is set:

2a) If you think the LSU is in a permanent/extreme locked state due to previous CPU not programming the reg5, then Goto unlock proceedure B

2b) Else Goto A.

3) If Full and BSY are clear, then CPU now has the LSU locked and can program the rest of the LSU registers to cause and outbound packet.

B) Unlock proceedure - write CBUSY and PRIVID

Hope that helps,

Travis

0 Chaitanaya Chhibbar over 13 years ago in reply to tscheck

Prodigy 80 points

Thanks Travis for the information. You reply was helpful.

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Clear SRIO LSU transactions using PRVID.