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c6678 Power Reduction - EVM6678L

Other Parts Discussed in Thread: UCD9222, TMS320C6678

Hello again!

This time around I'm trying to reduce the power consumed by the c6678 DSP.

I've powered down as many power-domains as I can within software (according to SPRUGV4A) as well as power down all 8 C66x CorePac's (as shown in SPRUGW0).

With all cores in standyby (controlled using XDS560v2 and CCS5) I am drawing around 1.088A and with the above power-reductions running on all 8 cores, I can only reduce the EVM's power to 0.840A.

Is this a realistic power reduction?  It seems very small considering I have supposedly (I may have done it incorrectly) made all 8 cores idle.

Any ideas/thoughts on how I can reduce the power of the device when it's not in use would be VERY helpful.

 

Thank you for you help!

  • As another option for power reduction, I have tried putting the chip into hibernation.  However, I have had little success with this.  Could this be because I'm using JTAG to load/run the program instead of using an EEPROM or flash memory?

     

    Thanks,

  • What power supply are you measuring this on?  Can you give details of the conditions (measurement of the temp of the heatsink at the center) what DSP activity is going on for each measurement, etc? 

    -Chad

  • I am measuring the total power consumption of the evaluation board with an in-line meter.  Not the best, but I was hoping to get an idea for what kind of power can be cut.

    Ultimately, I need to know how far these chips can be throttled down, in terms of watts (when idle/sleep/hibernation, whichever consumes the least).

    • The temperature under all tests was a steady 32.4*C, in the middle of the heatsink
    • Under the initial test (when load was higher), all DSP cores were held in a suspended state using a JTAG emulator
    • The Other tests simply initiated some form of power-savings routine on all cores (i.e. writing to a register, then calling the IDLE command).

    The tests really didn't go any deeper than that.  Perhaps I missed your point, did you need more/different info?

     

     

  • Can you clarify your measurement environment.  Based on your earlier posts I'm assuming that you are measuring the current at the power input connector from the 12V supply.  Is that correct? 

  • Hi Bill,

    Sorry for the confusion.  That is correct, I spliced the 12v power supply and put amp meter inline.

  • Like I mentioned before, these tests were just a means to an end.  I really just need to know what the power consumption of the c6678 is when it is in its lowest-power state, and how to get it there.

     

    Thank you for your help

  • Current measurements taken using the Beta EVM won't be completely representative of the final power reductions due to a number of factors. 

    • Current measurements on the 12V EVM power supply include not only the current for the C6678 but also the current of the supporting peripherals including the FPGA, the Ethernet PHY and the DDR memories.
    • The EVM power supply design was not optimized for efficiency.  While the design is adequate for evaluation and software development, board area was a larger factor then efficiency so the current draw on the 12V supply may not be representative of a customer production design.
    • Temperature is an important factor in determining the current requirement of the cores, especially in early silicon.  It’s difficult to hold the temperature in a steady state during these measurements.
    • The Beta EVMs were built with early non-production (TMX) silicon which is not representative of the final production silicon.  Early silicon will display a modest power reduction while production silicon will display a more pronounced reduction. 

     

    We will be performing a full characterization of the power of the C6678 in the coming month and will publish an appnote once that process is complete.  The target for the power appnote is June 2011.  In addition the PG2.0 version of the C6678 will include power-saving modes not present in the current version of the part.  Information on that version will be distributed in the near future.

    A more effective method of measuring the core power is to use the Fusion Power Designer software available on the TI website.  This software is used to design and monitor the operation of the UCD9222 on the EVM board.  Using a USB Interface Evaluation module (http://focus.ti.com/docs/toolsw/folders/print/usb-to-gpio.html) connected to PMBUS1 connector the temperature, power and current usage for the AVS and fixed 1.0V supplies can be monitored on a real-time basis providing a more precise measurement.

  • Hi Bill,

    Thank you for your detailed response.  Does the TMX silicon support hibernation mode?  If so, how would I go about putting the DSP into hibernation.  I have consulted the main TMS320C6678 datasheet, which seems to have the most information on the topic, but have not been able to successfully put the chip in hibernation.  Could you point me in the right direction, or provide a simple example of how this can be done?

    Thank you again,

  • Has anyone successfully put the c6678 chip into hibernation?  Following the information given in section 3.3.10 of the main c6678 datasheet (Power State Control (PWRSTATECTL) Register) I cannot seem to successfully get the chip to hibernate.  Apart from setting the correct PWRSTATECTL bit, is there anything that needs to be done to put the chip into hibernation?

     

    Thank you

  • Hi,

    We recently determined the correct sequence of steps to put the chip in one of the two hibernation modes. The sequence of steps for both hibernation 1 and hibernation 2 are almost the same except for one step. The sequence of steps are listed below:

    1. Power down domains of IPs that communicate with off chip masters (PCIe, SRIO, Hyperlink and Packet co-processor in that order)
         Note => Prior to powering down the above power domains, set  bits [15:12] of their respective PDCTL registers to 0000b. These bits are present in all PDCTL registers and will be documented in an updated version of the PSC user's guide.
    2. Disable LPSCs for EMIF16 and TSIP0/1 (in that order)
    3. Disable LPSC for debug_SS
    4. Set bits [15:12] in PDCTL of Corepac 0-7 to 0000b
         Then power down CorePac 1-7 power domains (Leave CorePac0 power domain ON)
    5. Configure DDR3 for hibernation: a) Set the RESETISO bit in MDCTL of DDR3 to enable reset isolation. b) Then put DDR3 in self refresh by programming LPMODE field in PMCTL register to 0x2 (Refer to DDR3 controller user's guide)
    6. Program bits [15:12] of MSMC power domain to 0001b to put MSMC RAM in retention mode for hibernation 1 OR program them to 0000b (completely OFF, no retention) for hibernation 2 mode. Then power down MSMC power domain => This is the only step different for hiber 1 v/s hiber 2.
    7. Configure all PLL controller reset inputs in RSCFG register as hard resets. You will have to unlock writes to RSCFG by first writing a key to RSTCTRL register (Refer to PLL controller users guide)
    8. Program PWRSTATECTL to reflect appropriate power saving mode (hiber 1 or hiber 2)
    9. Power down CorePac0 power domain

    Let me know if you have more questions.

  • Hello Aditya,

    Thank you for the detailed response describing hibernation entry.  I am in the process of coding a simple application and will reply with my results.

    Also, are there any other steps needed to bring the chip out of hibernation, or is the POR adequate?

     

    Thank you very much!

  • POR should be sufficient to bring the chip out of hibernation.

  • Great, thanks for the quick response, Aditya.

    I am having a few issues putting the chip into hibernation:

    1. What power domains are the EMIF16, TSIP, and debug_ss members of?  The reason I ask is that section 2.3.1 2.3.2 of Power Sleep Controller user guide seems to indicate that in order to trigger the module state transition, its corresponding power domain must be known.
      1. Current workaround: cycle through all power domains for each module transaction
    2. Powering down the CorePac module causes the program to freeze as it waits for the PTSTAT.GO[X] bit to clear (which it never does).

    Not sure if this would influence the situation or not, but I am using a JTAG emulator to run the program.  i.e. It's not running from a Flash storage device.  Could the emulator be causing the problem described in #2 above?

     

    Thanks again for your help!

    Best Regards

     

    P.S. I have attached a copy of my single source file for reference.

    1258.sleep.zip

  • EDIT: Sorry, that reference was supposed to be to section 2.3.2 of the Power Sleep Controller User Guide.

  • Also, since you've successfully put the chip into hibernation, what kind of power savings did you see?

    Thanks!

  • Hi, yes you need to know the power domain to turn off the module. Thanks for pointing that out. I will contact the PSC users guide owner to ensure this is put in either in the users guide or the device data manual.

    1. EMIF16: power domain# 0, LPSC# 3

        TSIP: Power domain# 0, LPSC# 4

         Debug_SS: Power domain# 1, LPSC# 5

    2. I have observed that powering down the CorePac will cause a CCS hang due to CPU stall. I am using an XDS560 emulator. I will have to check if the behavior you see is expected: The go bit should be set and CCS should essentially hang.

  • r_robotics, we still haven't reached the point of gathering and analyzing power data. As Bill mentioned we are currently in the process of performing a full characterization (including hibernation modes)  the results of which will be published in an app note by June 2011.

  • Aditya, thank you very much for your time and the detailed information which you've provided!  We greatly appreciate the support.

     

    best regards,

  • hello r_robotics:

            I have viewed through the post and got much help,but I still have several questions.

    I run the source file you provided but the current just drop from 1.01 to about 0.93,I think it is not significant enough for  hibernation mode,just as you said :

    "Powering down the CorePac module causes the program to freeze as it waits for the PTSTAT.GO[X] bit to clear (which it never does)" in your post,

    I think the corepacs do not go into sleep mode because it stopped when power down the core 1,and other cores has not been powered down at all! but I think your source is perfect ,and i can not find any useful information through the documents,can you give me some suggestions to help me get the DSP powered down?

    also ,have you successfully made the DSP go into the hibernation mode,what  result have you seen? what is the lowest current did you see?

    your source file has give me great help,thank you very much!

    looking forward for your reply!

  • Hello Aditya:

               now I need to know the power consumption in the hibernation mode,I can power down some power domains,but when I power down the core1's corepac,other cores  can not connect to the board also ,I think the cores have not got powered down,and the power consumption almost has been reduced. I want to know the different between powering down the core and other domains.I have tried the source code r_robotics posted in this post , my own code using CSL and the "psc.c"file found in ccsv5,those all have the same problem.

    exactly I want to know how to make the 8 corepacs powered down and what the power consumption is when the DSP is in hibernation mode,I am confused with it for many days ,I hope you can help me and give me some suggestions!

    thank you very much!