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256MB NAND flash in EMIF16

Wenjun Huang
Expert 1770 points


Why is there a limit on 256 MB NAND flash supported on the EMIF16 interface?

What is wrong with my explanation below?

THe EMIF16 has 16 lines (multiplexed) for data, address and control. Hence, 1 CS can address up to 32k of location. EMIF16 has 4 CS, hence it can address up to 4*32k = 128k of location. Each location can hold 16 bits = 2 Bytes. Hence, EMIF16 can hold 2B*128k =256kB?  

  • 0
    TI__Mastermind 42545 points

    NAND flash is not limited by the 64MB of address space associated with each chip select.  Since the addressing of the NAND flash is controlled by a software driver writing to address registers inside the NAND device larger devices can be accommodated by the EMIF16.  The 64MB limitation for each chip select is associated with devices that must be addressed by physical address lines such as NOR flash or SRAM.

  • 0 in reply to Bill Taboada
    Expert 1770 points

    Does that mean the datasheet on C66 p11 is wrong? It states that the EMIF16 supports up to 256MB of NAND flash.

    I have also read the EMIF16 document for KeyStone. It states that the EMIFD lines will be used for multiplexing as data, control and address lines. Hence, for 1 chip, it can have only up to 16 lines for addressing which is 64k (wrong for my previous post of 32k) of locations. 1 location can hold 2 bytes since the 16 lines is also used for data. Hence each chip can hold 128kB. There are 4 CS, hence the c66 should be able to hold 512kB. 

    Any error in my explanation above?

  • 0 in reply to Wenjun Huang
    TI__Mastermind 42545 points

    You are assuming that there is only one address cycle in a multiplexed address/data bus similar to how microcontrollers used to work.  NAND flash uses four address registers to provide the addressing needed for a read or write.  The table below shows the four registers used to create an access.  Since all of the accesses are done using a limited number of registers in the part it can address large blocks of memory without using many external address pins.  The EMIF memory limitations are based on the number of physical address pins available on the part but NAND doesn't depend on these address pins so the limitations don't apply.

    Cycle I/O[15:8] I/O7 I/O6  I/O5  I/O4  I/O3  I/O2  I/O1  I/O0
    First  LOW      CA7  CA6   CA5   CA4   CA3   CA2   CA1   CA0
    Second LOW      LOW  LOW   LOW   LOW   LOW   CA101 CA9   CA8
    Third  LOW      BA7  BA6   PA5   PA4   PA3   PA2   PA1   PA0
    Fourth LOW      BA15 BA14  BA13  BA12  BA11  BA10  BA9   BA8