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Disabling unused cores

Rashmi Tripathi
Prodigy 130 points

In a multicore DSP, is there a way to disable unused cores?

If yes,

- can you please explain how that can be done?

- do you know if disabling a core would result in power saving, and how this saved power would scale with more cores being disabled?

Thanks,

Rashmi

 

  • 0
    TI__Expert 6815 points

    Rashmi, please refer to the C66x CorePac users guide (SPRUGW0B) for related documentation.

    Each core has its own power down controller (PDC) that can be used to place a core in a low power state independent of others. Some aspects of power down are dynamic (example, L1P, L2 and caches. Sections 12.2.1 to 12.2.3 of SPRUGW0B). Others are software controllable as follows: (Sections 12.2.4 to 12.2.6).

    - To power down just the DSP, simply execute an IDLE instruction. Interrupts are required to wake up the DSP (Section 2.12.4).

    - To power down the entire CorePac, follow the steps for C66x power down (Section 2.12.5).

    - Powering down the CorePac driven by an external interrupt (Section 2.12.6)

    * Note that the Power sleep controller does not have the ability to clock gate a CorePac (the core clock domain is always ON).

    Disabling a core is expected to yield power savings. How much and how it scales with #cores is currently part of our ongoing power characterization effort.

  • 0 in reply to Aditya
    Prodigy 115 points

    Hi Aditya,

    using the TI RTOS on the C6672, I would like to deactivate one of the both cores through the DSP power. Can I have some explanation on where i have to do it in the OS?
    Do you have any sw workflow description from the "ROM boot loader" to the launch of TI RTOS ?  (TI RTOS is flashed in a NAND flash connected to SPI).

    Thank you