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C6678 DDR3 questions

jschipp
Intellectual 350 points

I have the following questions with regards to the DDR3 interface on C6678.

 

The goal is to get the interface to work at 1600MT/s using 4 x16 memory devices in parallel. This may not be possible because of the issues listed below which I hope you can help clarify.

 

1) Advisory 9 in the Errata indicates that DDR3 memory has a problem with read leveling. Workaround 2 is not an option because I am using fly-by termination and can not get the maximum skew under 1".  So the best is 800MT/s with this topology.  Workaround 1 is the only option to use auto balancing. The question is that what is meant with "derate for long term use". In my case the memory devices are not on a module but directly on the board and I expect that there may be some gain in doing that. What factors will prevent it from working long term?

 2) The DDR3 Design Requirements document (sprabi1a) does not show how to place the memory devices with respect to DSP and what the various trace impedances should be. Given that there are already problems with this interface is it possible to get this info from TI when using 4 x 16 memory devices in a 64-bit bus concept. It only mention loosely in the document that trace impedance is in general 50 ohm on a PCB. For the DM8148 this info is available in far more detail which is very helpful.

 

3) Do you have any time line on when TI plan to have a fix for the memory interface and if this interface will run at 1600MT/s when using 4 x 16 memory devices on the board?

  • 0
    TI__Mastermind 30825 points

    Jschipp,

    There is an Errata update that's about to be released, in which we have an advisory stating that we will only be able to support up to 1333MT/s.  Note this is for PG1.0 of the device, we have changes in place to correct the issues where have been seeing at 1600MT/s for PG2.0 of the device.

    That said I'd assume that they'd want to design this to support 1600MT/s for when PG2.0 comes out so they could step up to that speed.  I'll have someone address that.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Intellectual 350 points

    Chad,

    Thank you for commenting.  Are you you able to specifically address the following?

     

    Advisory 9 ....The question is what is meant with "derate for long term use". In my case the memory devices are not on a module but directly on the board and I expect that there may be some gain in doing that. What factors will prevent it from working long term? Is this still necessary with PG2.0?

     2) The DDR3 Design Requirements document (sprabi1a) does not show how to place the memory devices with respect to DSP and what the various trace impedances should be. Given that there are already problems with this interface is it possible to get this info from TI when using 4 x 16 memory devices in a 64-bit bus concept. It only mention loosely in the document that trace impedance is in general 50 ohm on a PCB. For the DM8148 this info is available in far more detail which is very helpful.  Is there any additional documentation that would be helpful in memory placement/layout guidelines?

     

    3)  Do you have an expected date for samples/release on PG2.0?

     

    Best Regards,

    John


  • 0 in reply to jschipp
    TI__Mastermind 30825 points

    John,

    On Advisory 9, Workaround 1 is listed as

    The DDR3 PHY in the device has the ability to complete auto-leveling of the write
    leveling values and the read DQS gate training values separate from the read data eye
    training. Then a single value is used as the read data eye sample point. This solution is
    functional on standard DDR3 fly-by layouts. It has been shown to operate robustly at
    DDR3-1333 when connected to a UDIMM but this rate may need to be derated for
    long-term operation.
    This mode is enabled by setting bit 9 (0-indexed) of the DDR3_CONFIG_REG_23 at
    address 0x02620460. The lower 8 bits (bits 7:0) will be loaded with the read data eye
    sample point. At this time, we recommend programming this value to 0x50.
    Auto-leveling is enabled after bit 9 of the register DDR3_CONFIG_REG_23 above is
    set.

    In this case we're saying that we may not necessarily be able to guaranty this at 1333 on UDIMMS and this may need to operate slower than 1333 for guaranteed results.

    We're working on updating the DDR3 design guidelines to make it more thorough.

    PG2.0 Samples Dec/Jan timeframe, TMS mid 2012.