We've been trying to talk to an FPGA over EMIF-16 from a C6678 EVM and are having some problems, which we're working through. One thing we do need is to completely turn off read and write caching and prefetch for the relevant memory region, since the FPGA is memory mapping "live" registers and we want to minimise the age of the data read.
It's clear that we want to clear the Memory Address Register MAR116. I can do this via SYS/BIOS ti.family.c66.cache and all is OK.
However, my first effort used the CSL cache functions, and I found this extremely confusing. I'm recording it here in case anyone else finds this helpful.
Basically, there seem to be FOUR bits in the MAR:
pc permit caching
pcx Is address cacheable in external cache (MSMC)
pfx Is address prefetchable
wte Write-through enabled.
But the CorePac user's guide (rev B, as listed currently on the ti.com tech documents list) lists only pc and pfx.
So when I tried using CSL_disableCache (which writes pc only) and then CSL CACHE_getMemRegionInfo to see whether the region was cacheable (which returns pcx and pfx only) I concluded the former was not working! You have to look quite carefully at CACHE_getMemRegionInfo to see that it's reporting something different.
Also, the reset state of the MAR seems to be 0x0c, i.e pc=0 but pcx=1. Does this make the EMIF cacheable or not? I can't find any documentation about that, though I'm now guessing "no". For our needs it doesn't matter, as I think we just want all bits to be 0, but it would help me understand some of the behaviour we saw in our early testing if I knew whether or not the cache had been on.
Just to muddy the waters further, when you view our EMIF region in the CCS Debug Memory Browser in shows the L1D and L2 cache checked. That initially seemed to indicate to me that the cache was on. I've already redefined the region in the GEL memory map as read|write|port. If the debugger can't definitively tell, how am I supposed to know?
