PCIE on C6678

Hi, please refer to Section 2.11.2 PHY Loopback in the PCIe users guide (SPRUGS6A) for details on PHY loopback. The procedure is similar to PIPE loopback, but you also need to set both the Transmit and Receive paths in loopback mode to enable PHY loopback mode. These can be controlled in the SERDES Configuration Lane x Registers.

Also it is recommended to set loopback before link training. Otherwise, any transactions that were not looped back will cause sequence numbers to increment on transmitter but not on receiver. This will cause all following transactions to be dropped because of sequence number mismatch.

Yes i did that , but there is also no results .  It is possible that we perform PHY Loopback without link training ?

Sorry, I did not quite understand "there are no results". Can you elaborate what it is that you observe? Let me get a PCIe expert to help you out.

i mean by " there is no results ", the fact of that no data is back to the Root complex after sending 1 data

Thank You Very much and i hope you arrive to perform the internal loopback quickly

For the other kind of loopback , i do not have a support to connect the  2 shannons , and i m afraid from doing it just with  lanes welding ( RX1-- TX1  and RX2 --- TX2 ) , for

reasons   of  high frequency of transfer , fear of endommaging the two C6678 EVM platforms when welding , safety of platforms   .....etc

So if you can adviser me of a method to connect the two shannons or to consolidate me of the safety of the previousely mentionned  operation

Sincerely,

Younes

Younes,

If I understand correctly, you have two Shannon EVMs to be tested, right?

In that case, I think you could try the Dual EVM Break Out Card (CI2EVMBOC) for the two Shannon EVMs connection. You can find more info in the following page:

http://processors.wiki.ti.com/index.php/CI_Dual_EVM_Break_Out_Card

It could be ordered in TI estore and It supports the high speed interface communication like SRIO, PCIe, SGMII and AIF.

It should give you the solid connection between the PCIe peer-to-peer (RC-to-EP) connection. And the PCIe example in the MCSDK package can also be tested directly in this two-board setup.

And you could test more features in PCIe like configuration transactions, which is not supported in neither internal or external loopback mode. Hope it helps.

Sincerely,

Steven

Thank you very much Steven , realy you gived me interesting information ,

but actualy , i have to connect one C6678 and an other processor (FPGA),  so the solution i need is not like the " Dual EVM Break Out Card "

so if you have any solution for me

Sincerely,

Younes

Younes,

If your FPGA board also has the PCIe male edge connector, you can use the TMDXEVMPCI on your C6678 EVM and plug both FPGA and C6678 into the PCIe backplane/motherboard which supports the communication between the boards. And you can set one as RC and another one as EP for the testing. There could be lots of choices on the market for the backplane/motherboard and you can do some research on that.

For the single board, external loopback testing, if you have concern about the safety/reliability issue, you probably can try the some AMC break out cards like the following one:

http://silicontkx.com/SMA-AMCULTRA9000.html

It gives you the capability of connecting each pins in the AMC connector of C6678 including PCIe pins and you can use SMA cables for the external loopback connection, which is reliable and easier for your testing.

Hope it helps.

Sincerely,

Steven

Steven,

I am doing something similar, connecting the C6678 EVM with an FPGA.  I have the FPGA eval board with a male PCIe edge connector and wanted to use the TMDXEVMPCI for the C6678 to connect the two.  I'm having a terrible time trying to locate a passive backplane that would allow the TMDXEVMPCI to be wired as an RC.  From what I can tell, the TMDXEVMPCI is configured as an EP card. 

Does TI have knowledge of a solution that allows the TMDXEVMPCI to act as the RC in a passive backplane?  Or, am I missing something.

Thanks for your help.

Andrew,

I think you are correct that on the backplane, the PCIe slots are connected to the downstream ports of the PCIe switch on the backplane which are used for PCIe EPs.

I am not sure if the C6678 with TMDXEVMPCI could be plugged into the SHB/SBC slot and used as one host/RC. But it seems like the PCIe slots on the backplane are used for EPs only.

All,

There is some update for the PCIe internal loopback mode setup in KeyStone I devices. Please take a look and hope it is working for your testing with single EVM setup:

PHY loopback configuration for KeyStone I devices:

• Please follow the steps (up to Step 7) described in Section 2.11.1.1 ‘‘Initialization Sequence’’ for RC mode.
• Before executing Step 8, we need to configure the SerDes configuration registers to set Transmit and Receive paths to be in loopback mode.
  • Enable TX loopback and RX loopback in SerDes Configuration Lane 0 Register (SERDES_CFG0[TX_LOOPBACK]=0x2 and SERDES_CFG0[RX_LOOPBACK]=0x3).
  • Disable loss of signal detection in SerDes Configuration Lane 0 Register (SERDES_CFG0[RX_LOS]=0).
• Do the same configuration for SerDes Configuration Lane 1 Register if testing in two lanes mode.
• Then initialize link training (Step 8 in Section 2.11.1.1).
• Before checking link training status (Step 9 in Section 2.11.1.1), we need to skip Detect state in LTSSM and force link to begin with POLL_ACTIVE state.
  • Set 0x2 (POLL_ACTIVE state) in LNK_STATE field of Port Force Link Register (PL_FORCE_LINK[LINK_STATE]=0x2).
  • Set 0x1 in FORCE_LINK field of PL_FORCE_LINK register to force the link to the state specified by LINK_STATE field (PL_FORCE_LINK[FORCE_LINK]=0x1).
• Then insure link training completion (Step 9 in Section 2.11.1.1)
• With the initialization above, PCIESS should be configured in PHY loopback mode.