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Uart in Interrupt Mode ?

Hello,

I am trying to run uart in interrupt mode on my C6678L EVM. I want to use USB debug cable (not DB-9 one) for doing this. My application deploys Sys-Bios . Here is what I've done:

  1. I've programmed Corepac Intc: Enabled hwi 4, enabled primary event 63, assigned an interrupt handler to it.
  2. I 've programmed Chip Level Intc 0: I enabled System Interrupt 149 (Uart Rx Event), and mapped it to channel 3.
  3. I got cpintc_test example as referans design for me.
  4. I tested my application using test methods in 'cpintc_test', and test ran successfully : My test was including System Interrupt 149 mapped to channel 3, primary event 63 and hwi 4 as I described above. The interrupts were driven manually using STATUS_SET_INDEX_REG of CpIntc. And I saw interrupt hadler working and test running successfully.
  5. I programmed platform uart peripheral using platform library. The only modificaiton that I did was enabling ERBI interrupt. I recompiled platform_lib and deployed it in my application.
  6. But when I try to send any character from hyperterminal (with settings: 115200 bps, parity even, Flow control none ), the PC does not hit to the interrupt handler.

Do I need to do any extra modification at platform library other than step 5 for achieving my goal ?

Thanks in advance,
koray

  • Koray,

    Based on the section 2.8 "Interrupt Support" in UART user guide, URXEVT and UTXEVT are DMA events, not CPU events.

    So instead of using system event #149 (URXEVT), please give a try of event #148 (UART interrupt). The receive data event (RDAINT) along with other UART interrupt requests are connected to that single interrupt event, which is forward to chip-level interrupt controller event #148 and then to CPU.

  • Hi Steven,

    I changed the system interrupt number to 148, but still unable to see the interrupts working.
    Also, I have some extra questions:

    1. At the link below, it says that jtag and Uart functionality can be used simultaneously at XDS100v2 emulators. And it says it is not officially supported. Does that mean that I shouldn't use jtag and Uart simultaneously ?
      http://processors.wiki.ti.com/index.php/XDS100#Q:_Can_I_use_port_B_as_a_UART.3F
    2. And on the 6678EVM, emulator is XDS100v1 , not v2.  Is Uart functionality valid in this version ? Beause, in the link above, it seems that Uart functionality is not supported at v1 type emulators.

    regards,
    koray.

     

  • Koray,

    For the XDS100 emulator, "not officially supported" means the functionality does not be verified for XDS100v2, since it requires the customized hardware design.

    On C6678 EVM, the XDS100 should support both of JTAG and UART simultaneously since they are using different channels (Channel A&B) in the USB-JTAG converter. Please double check the COM_SEL1 that if shunts installed over COM_SEL1.3-COM_SEL1.1 and COM_SEL1.4-COM_SEL1.2 for the mini-USB connection. Please refer to the EVM manual for more details.

    For the UART interrupt, please double check if DLAB=0 in LCR register when you set 1 ERBI field of IER register.

    And when UART receives data, please also check the IIR register to see if the receive interrupt has been recorded in the registers. If there is no pending interrupt, it might indicate the UART interrupt has not been setup correctly.

    If you would like, you can also share your test case here and we can try to verify it in our setup as well. 

  • Hi Steven,

    Please find the attached project that I built for you. I also added the platform library that I am using.

    I checked the shunts, they are at the right place.
    I checked DLAB bit at LCR register, it is 0.
    I checked the IIR register when I stop PC manually, it always remain at 0. It seems there is a problem at UART setup as you suggested.

    regards,
    Koray0830.intcDeneme.zip


     

  • Hi Steven,

    I also attached the UartInit() function of the platform library that I am using. Please find it.

    Regards,
    Koray.

    void UartInit(void)
    {
        //      Allows access to the divisor latches of the baud generator during a 
        // read or write operation (DLL and DLH)
        CSL_FINS (hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_ENABLE);
        //      Break condition is disabled.
        CSL_FINS (hUartRegs->LCR, UART_LCR_BC,   CSL_UART_LCR_BC_DISABLE);
        //      Stick parity is disabled.
        CSL_FINS (hUartRegs->LCR, UART_LCR_SP,   CSL_UART_LCR_SP_DISABLE);
        //      Odd parity is selected
        CSL_FINS (hUartRegs->LCR, UART_LCR_EPS,  CSL_UART_LCR_EPS_ODD);
        //      No PARITY bit is transmitted or checked
        CSL_FINS (hUartRegs->LCR, UART_LCR_PEN,  CSL_UART_LCR_PEN_DISABLE);    
    
        // Set the baudrate,for accessing LCR[7] should be enable 
        hUartRegs->DLL  = DLL_VAL;
        hUartRegs->DLH  = DLM_VAL;
    
        // Allows access to the receiver buffer register (RBR), 
        // the transmitter holding register (THR), and the
        // interrupt enable register (IER) selected.
        CSL_FINS (hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_DISABLE);
        // Even Parity is selected
        CSL_FINS (hUartRegs->LCR, UART_LCR_EPS, CSL_UART_LCR_EPS_EVEN);
        // Parity Enable 
        CSL_FINS (hUartRegs->LCR, UART_LCR_PEN, CSL_UART_LCR_PEN_ENABLE);
     
        // Disable THR, RHR, Receiver line status interrupts
        //CSL_FINS (hUartRegs->IER, UART_IER_ERBI,  CSL_UART_IER_ERBI_DISABLE);
        CSL_FINS (hUartRegs->IER, UART_IER_ETBEI, CSL_UART_IER_ETBEI_DISABLE);
        CSL_FINS (hUartRegs->IER, UART_IER_ELSI,  CSL_UART_IER_ELSI_DISABLE);
        CSL_FINS (hUartRegs->IER, UART_IER_EDSSI, CSL_UART_IER_EDSSI_DISABLE);
    
        CSL_FINS (hUartRegs->IER, UART_IER_ERBI,  CSL_UART_IER_ERBI_ENABLE);
    
    
        /* If autoflow control is desired, 
        * write appropriate values to the modem 
        * control register (MCR). Note that all UARTs 
        * do not support autoflow control, see 
        * the device-specific data manual for supported features.
        * 
        * MCR
        * ====================================================
        * Bit  Field   Value   Description
        * 5    AFE     0       Autoflow control is disabled
        * 4    LOOP    0       Loop back mode is disabled.
        * 1    RTS     0       RTS control (UARTn_RTS is disabled, 
        *                      UARTn_CTS is only enabled.)
        * =====================================================
        * 
        * 
        */
    
        hUartRegs->MCR = 0;
    
        /* Choose the desired response to 
        * emulation suspend events by configuring 
        * the FREE bit and enable the UART by setting 
        * the UTRST and URRST bits in the power and 
        * emulation management register (PWREMU_MGMT).
        * 
        * 
        * PWREMU_MGMT
        * =================================================
        * Bit  Field   Value   Description
        * 14   UTRST   1       Transmitter is enabled
        * 13   URRST   1       Receiver is enabled
        * 0    FREE    1       Free-running mode is enabled
        * ===================================================
        * 
        */
        hUartRegs->PWREMU_MGMT = 0x6001;
    
        /* Cleanup previous data (rx trigger is also set to 0)*/
        /* Set FCR = 0x07;        */
        CSL_FINS (hUartRegs->FCR, UART_FCR_FIFOEN,   CSL_UART_FCR_FIFOEN_ENABLE);
        CSL_FINS (hUartRegs->FCR, UART_FCR_TXCLR,    CSL_UART_FCR_TXCLR_CLR);
        CSL_FINS (hUartRegs->FCR, UART_FCR_RXCLR,    CSL_UART_FCR_RXCLR_CLR);
        CSL_FINS (hUartRegs->FCR, UART_FCR_DMAMODE1, CSL_UART_FCR_DMAMODE1_DISABLE);
        CSL_FINS (hUartRegs->FCR, UART_FCR_RXFIFTL,  CSL_UART_FCR_RXFIFTL_CHAR1);
    
        return;
    }

  • Koray,

    Thanks for the example test project. I will look into it and hope to get back to you soon. 

  • Hi Koray,

    As your example test, check your code about IER. I saw your interrupt is disable in code.

  • Koray,

    I modified your example and attached below for your reference. 

    Basically, we have to specify the baud rate and enable ERBI bit in IER register.

    The modification is based on the "platform_test" project in the PDK.

    And the testing could be completed by using USB cable (XDS100 channel B). The XDS100 supports both JTAG and UART communications simultaneously.

    The following link could be helpful as well.

    http://processors.wiki.ti.com/index.php/Using_the_serial_adapter_of_XDS100

    6354.main.zip

  • Hi Steven,

    Sorry for responding late. I was on vacation for some time .

    I analyzed your project and found out that the problem at my project was PLL initialization. I haven't done any platform initialization and also PLL initialization. When I initialized it, it worked !!

    Your project helped me to see the PLL initialization part.

    By the way, I modified my platform library and set ERBI bit, baudrate there. That's why you didn't see any initialization code for these settings in my project. It was already included in my platform library and platform library file was in the project folder.

    Thanks and regards,
    koray.