Hi,
I have SRIO Unit test code which does transfers successfully to the host processor. It uses the SRIO/CPPI/QMSS driver from the pdk_C6678_1_0_0_17.
1. I noticed that the SIZE_HOST_DESC is defined to be 48. But the structure defined in cppi_desc.h has 13 elements so, I expect sizeof(Cppi_HostDesc) to be 52. Moreover, I think this value is required to be the next higher multiple of 16, so should not the SIZE_HOST_DESC be 64? At some places in the example code, SIZE_HOST_DESC is used, while sizeof(Cppi_HostDesc) is used at other places. The sample application works fine, but I wonder if this is to be expected.
/**
* @brief CPPI host descriptor layout
*/
typedef struct {
/** Descriptor type, packet type, protocol specific region location, packet length */
uint32_t descInfo;
/** Source tag, Destination tag */
uint32_t tagInfo;
/** EPIB present, PS valid word count, error flags, PS flags, return policy, return push policy,
* packet return QM number, packet return queue number */
uint32_t packetInfo;
/** Number of valid data bytes in the buffer */
uint32_t buffLen;
/** Byte aligned memory address of the buffer associated with this descriptor */
uint32_t buffPtr;
/** 32-bit word aligned memory address of the next buffer descriptor */
uint32_t nextBDPtr;
/** Completion tag, original buffer size */
uint32_t origBufferLen;
/** Original buffer pointer */
uint32_t origBuffPtr;
/** Optional EPIB word0 */
uint32_t timeStamp;
/** Optional EPIB word1 */
uint32_t softwareInfo0;
/** Optional EPIB word2 */
uint32_t softwareInfo1;
/** Optional EPIB word3 */
uint32_t softwareInfo2;
/** Optional protocol specific data */
uint32_t psData;
}Cppi_HostDesc;
2. When I try to bring over the SRIO driver to other application, the SRIO transmit does not work. The Srio_socSend() returns without any error, but the Srio_txCompletionIsr is never called. Now, I copied over all configurations from the working unit test code, and I cannot see anything that I missed.
One difference I noticed is that the host buffer descriptors addresses for the unit test application were under L2SRAM for Core0. I am only using Core0 for now. But for the final application the address are 0x1c200b60, 0x1c200b90 etc. Per the 6678 datasheet these fall in the reserved address range 17F08000 to 1FFFFFFF.
The buffer descriptors are allocated by the CPPI/QMSS driver, so I wonder if this is to be expected either.
I think, I came across some requirement about a heap for CPPI. Note that the system heap was moved over from the multicore shared memory to DDR3. And I have only one heap defined. With the same change on the unit test code, still works. So I assume the heap is ok.
Thanks!
Shivang
