EVM 6657 Gauss platform Interface DSP to an external Telephony card on SPI

The CS1 of the SPI interface is used for the FPGA Firmware Update SPI interface.  This is the interface that is used to modify registers in the FPGA.  This interface can be disabled to allow the expansion connector to drive the SPI data input.  Look at the FPGA FW Update SPI Interface Control register on page 85 of the technical reference manual of the C6657 EVM for more information.  Remember that once you have disabled the interface to the FPGA you won't be able to access the registers in the FPGA again until after an FPGA reset has occurred.  For more information on modifying the FPGA registers please refer to the following post.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/199537/749274.aspx#749274

Does this really disable SPI? I still see that data is asserted. Note: Default value of this register is 0x00. (meaning disabled). I wrote 0x00 and it does not disable SPI data pin from FPGA. 

I want to make sure, I understood your suggestion correctly. 

Register Address: SPI Base + EDh
Register Name: FPGA FW Update SPI Interface Control Register
Default Value: 00h
Attribute: Read/Write
Bit Description Read/Write
7-0
FPGA FW Update SPI Interface Enable Control: These bits are used
to enable/disable the FPGA FW Update SPI Interface. If the value of
this register be set to 68h, the FPGA FW Update SPI interface would be
enabled. All the other values set to this register would disable the FPGA
FW Update SPI interface.
68h: FPGA FW update SPI interface is enabled.
Others: FPGA FW update SPI interface is disabled.
DSP_GPIO[12] is mapped to FPGA_FW_SPI_CLK.
DSP_GPIO[13] is mapped to FPGA_FW_SPI_CS#.
DSP_GPIO[14] is mapped to FPGA_FW_SPI_MOSI.
DSP_GPIO[15] is mapped to FPGA_FW_SPI_MISO.

I think there is a typo in the manual "Technical Reference Manual TMDXEVM6657L SPRUHG7 - Revised May 2012", Page 84.

Register Address: SPI Base + EDh  

It should be SPI Base + 0Eh

In any case, this configuration seems not helping us to disable SPI. Pl. advise. 

Hi Harikrishna,

After reviewing the design with the manufacturer we found that the SPI_CS1 is dedicated to communications with the FPGA and can't be disabled.  That SPI chip select is not available for use on the 80pin connector.  We don't have a work around that would allow the 80pin connector to use SPI_CS1 at this time.  The only work around that we can offer requires modification to you EVM and the use of SPI_CS0.  This will eliminate the use of the SPI NOR memory U260 and will use the DSP_EMIFCE2Z pin on the 80pin connector to bring SPI_CS0 to the daughtercard.  The work around is described in the attached document.  Once you've made this change you should be able to use SPI_CS0 to operate the SPI interface on the daughtercard.  Remember that the SPI chip select will now be on pin 41 (DSP_EMIFCE2Z) of the 80pin connector and that you will need to add a pull up resistor to 1.8V for the chip select signal.

Regards, Bill

4555.SPI work around.pdf

Hi Bill,

  I appreciate your help. We are going ahead with the hardware change suggestion. Meanwhile I got a question regarding SPI NOR Flash. I want to make sure about the functionality of NOR Flash. When is it needed? When we boot from JTAG (USB), do we need Flash memory? I hope there is no effect on peripherals drivers initialization (like DDR3) etc.. Hope the GEL files take care. Can you throw some details on SPI NOR Flash functionality and anything it does after bootup, any other info. 

Regards,

Hari

Hi Hari,

The SPI NOR flash contains the out-of-the-box demo code that runs when you power the EVM.  If you are loading your own code using code composer then you won't need the SPI NOR flash. You will need to incorporate any initialization into your own code to be sure that the part operates correctly but you will need to do that for your own system anyway.  The basic initialization of things like the PLLs and the DDR3 is performed by the IBL code which is in the I2C memory. 

Regards, Bill

Hi Bill,

I need to use this SPI for external connection.  Before I make the hardware mod instructed here:

http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/639/4555.SPI-work-around.pdf

I attach a scope probe to pin one of U260, DSP_SSPCS0.  There is no activity when I transmit to SPI.

But if I change dip switches to SPI boot, and reboot the EVM, I can see SPI access with CS0 on o-scope.

What might be my problem?

Thank you.

Regards,

Steve

Here are my SPI register values:

20bf0000 00000001 01000003 00000000 00000000

20bf0010 01000200 01010E01 00000000 00000102

20bf0020 00000000 00000000 00000000 00000000

20bf0030 01010F03 00000000 00000000 10020000

20bf0040 80000000 80000000 08080000 00000001

20bf0050 00010F08 00000000 00000000 00000000

20bf0060 00000000 00000000 00000000 00000000 

Hi,

Can I change the SPI CS pin configuration to active high (by default, it is active low), means the SPI communication would start when the CS pin will be driven high so that the FPGA is not triggered while on the target side, an inverter would invert the logic level for CS signal and would enable the SPI communication with the target board?  I am aware of the fact that the timings for the CS signal have to be handled properly for proper communication.

Hi Prashant,

The SPI controller in the C6657 doesn't give you the ability to invert the SPICSn signal. If you are communicating with an FPGA, I suggest you reprogram the FPGA to look for the CS going low. Alternatively, you can use an external resistor but, as you stated, you will have to be sure the timing matches the C6657 data manual. 

Regards, Bill

Hi Bill,

I have a C6670 which seems to have such configuration.  From my knowledge, CS pin is by default pulled up and the data is transmitted when the pin goes low. So, in my case I will invert the configuration such that by default, CS pin is always low and for data transmission it has to go low. Now, will the FPGA send data in this case since the CS pin is always low and the clock is continuously coming? Or is it the case that it is edge triggered (for high to low) such that it won't send any data although CS is low?

And if in case the FPGA sends data even in this configuration, is there any way to change its settings so that it won't send the data?

Hi Prashant,

Where did you find the configuration setting to change the polarity of the CS in the C6670? I'm afraid I won't be able to help you with any questions on the FPGA. You will  have to get that information from the FPGA designer. It could be programmed to operate in different ways. 

Regards, Bill

i am using a C6670 Evaluation DSP kit.As mentioned in the earlier post the intention is to interface external ADC using SPI interface.Since SPI interface is used by NOR or FPGA ,i was looking at alternative techniques before proceesing with any hardware related workaroud as mentioned in forums.

In The Keystone SPI datasheet (sprugp2a.pdf file),i found the following description under The SPI Default Chip Select Register (SPIDEF) .

Chip Select Default pattern. In master mode, the bit position i in this field determines the SPISCS[i] pin state when no transmissions are currently performed. It allows the user to set a chip select pattern which deselects all the SPI slaves

Bit position i in this field:
0 = The corresponding SPISCS[i] pin is cleared to 0 when no transfer occurs.
1 = The corresponding SPISCS[i] pin is set to 1 when no transfer occurs.

thus if i keep the pin to 1 when no transfer occurs it will provide a high to low transition when i initiate the transfer.I have verified this by observing the CS signal on the oscilloscope.

Thus assuming FPGA requires a high to low transition,i will configure 0 in the bit position 0 in the SPIDEF register.hence the CS pin will be 0 when no transfer occurs and will be high when a data transfer is initiated.

I will provide the CS pin output to inverter and then to ADC i am using.This ADC will be triggered by a low to high transition.I also plan to tune the C2TDELAY and t2CDELAY to ensure that at no point of time i am accessing the registers on the FPGA

One concern with this approach is that when CS is low ,does this mean that FPGA will start sending data or is FPGA SPI data transfer initiated by rising or falling edge.As mentioned in the earlier post can you provide us suitable links or redirect us  to support forums which we can post our quiries regarding the FPGA

Related query is that if  SPICLK pulse generated continuously or it is generated only during the time when the CS goes high/low indicate a SPI transfer.

Even if the FPGA is active when CS is low/high ie it ,can we assume that no SPI transfer occurs as long as no SPICLK pulses are transmitted .This can be controlled by us through software when we enable CS pin.

Thus if we can assume that clock pulses are generated only when CS is active,FPGA will never receive the clock data and only external ADC will receive the pulses and send us the data.