Hello,
We would like to interface TMS320C6678 with an ADC (>=80MSPS) and >=14 bits. Is it possible? What are our options?
Thank you.
Basu
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Hello,
We would like to interface TMS320C6678 with an ADC (>=80MSPS) and >=14 bits. Is it possible? What are our options?
Thank you.
Basu
There's no direct interface for TMS320C6678 to ADC. ADC's in general either have a serial interface or uPP interface, which the TMS320C6678 does not have. The best option would be to use an FPGA as an interface between the DSP and the ADC. The FPGA could connect via one of the many available IPs on the C6678 and the appropriate IP for the chosen ADC.
Best Regards,
Chad
Thank you Chad,
Will we be able to use 6657 EVM with a high speed (like mentioned in the previous post) ADC? May be use its uPP?
Basu
The uPP pins, which are muxed with the EMIF16 pins, are brought out to the 80-pin header on the EVM.
You have the ability to build a board with ADC on it that plugs into the EVM connecting via the uPP.
Best Regards,
Chad
That's really a very low speed solution, intended for monitoring and controlling of power rails. This is not the general type of ADC/DAC you'd see used w/ a high performance DSP, but more typically used with a micro controller such as an MSP430.
Not that I2C is a very low performance IO ~400KHz operational speed is what we support.
Best Regards,
Chad
Hi Chad:
For the C6657 how would you recommend interfacing a 100-125 MSPS 14 bit ADC? My understanding is that the uPP has a maximum rate of 75 MSPS so I don't think we could use it for a 100-125MSPS ADC.
Thanks in advance for your help,
Brett
You would need to have an ADC that interfaced to an IP that's fast enough to support that rate, or possibly use an FPGA in between as an interface to an higher data rate IP such as SRIO, PCIe, etc.
Best Regards,
Chad
Am I correct that the uPP will not support 125MSPS at 14 bits?
Any specific suggestions regarding interfacing to the SRIO, PCIe or Hyperlink with an FPGA?
Thanks,
Brett
If my understanding is correct in that it's 14bits / sample, and it probably would be packed in 16bit data in the uPP interface, which would only support 75MHz operation on 16bit data, then yes your understanding is correct in that it would not support that sampling rate.
I'd go with SRIO or PCIe depending on your comfort level. Both can support 5Gbps data traffic over a single lane implementation. Hyperlink would be overkill for this type of application.
Best Regards,
Chad